Bottom electrode structure in memory device

A method of forming an integrated chip, the method comprising:

• forming an opening to extend through an insulating structure and expose an interconnect within a dielectric structure over a substrate;
• forming a reactivity reducing coating directly between sidewalls of the insulating structure forming the opening;
• forming a bottom electrode layer on the reactivity reducing coating and over an upper surface of the insulating structure, wherein the bottom electrode layer has a first electronegativity that is less than or equal to a second electronegativity of the reactivity reducing coating as measured by numerical values according to Pauling's scale and wherein a difference between the first electronegativity and the second electronegativity is greater than 0.2;
• forming a data storage element over the bottom electrode layer;
• forming a top electrode layer over the data storage element;
• and
• forming a memory device by removing parts of the top electrode layer, the data storage element, the reactivity reducing coating, and the bottom electrode layer.

A method of forming an integrated chip, the method comprising:

• forming a diffusion barrier over an upper surface of an interconnect within an inter-level dielectric (ILD), the upper surface facing away from a substrate;
• forming a reactivity reducing coating onto an upper surface of the diffusion barrier;
• forming a bottom electrode layer on and in contact with an upper surface of the reactivity reducing coating that faces away from the reactivity reducing coating, wherein the bottom electrode layer has a first electronegativity that is less than or equal to a second electronegativity of the reactivity reducing coating as measured by numerical values according to Pauling's scale;
• forming a data storage element on and in contact with an upper surface of the bottom electrode layer that faces away from the reactivity reducing coating;
• forming a top electrode layer over the data storage element, the top electrode layer being separated from the bottom electrode layer by the data storage element;
• and
• performing one or more etching processes to remove parts of the top electrode layer, the data storage element, the reactivity reducing coating, and the bottom electrode layer.