US 12,707,700 B2 · Contact arrangements for transistors

Abstract

A variety of applications can include apparatus having one or more transistors with a contact arrangement to significantly mitigate a parasitic capacitance between one or more contacts to an active area of the transistor and a gate of the transistor. One or more contact arrangements can include a contact to an active area in a position beyond a boundary of an end of the gate along a first direction, where the gate is structured along the first direction. One or more other contact arrangements can include two contacts to an active area in positions beyond boundaries of two opposite ends of the gate along a first direction. Arrangements can include a metal silicide region coupling two contacts to each other in an active region with the two contacts in positions beyond boundaries of two opposite ends of the gate along a first direction.

Claims20

Dependent claims

A transistor comprising:

a first source/drain region in a first active area;
a second source/drain region in a second active area;
a gate located above a channel structure between the first source/drain region and the second source/drain region, the gate having a horizontal length defined by and bounded by two boundaries along a horizontal direction parallel to the first source/drain region and the second source/drain region and having a width perpendicular to the horizontal length substantially bounded by the first source/drain region and the second source/drain region;
one or more first contacts to the first active area, the one or more first contacts positioned above the first active area and distributed in one or more regions of the first active area along the horizontal direction beyond the two boundaries;
and
one or more second contacts to the second active area.

3 more elements

A memory device comprising:

a memory array;
and
a periphery region to the memory array, the periphery region including one or more circuits, the one or more circuits including a transistor, the transistor including:
a first source/drain region in a first active area;
a second source/drain region in a second active area;
a gate located above a channel structure between the first source/drain region and the second source/drain region, the gate having a horizontal length defined by and bounded by two boundaries along a horizontal direction;
direction parallel to the first source/drain region and the second source/drain region and having a width perpendicular to the horizontal length substantially bounded by the first source/drain region and the second source/drain region;
one or more first contacts to the first active area, the one or more first contacts positioned above the first active area and distributed in one or more regions of the first active area along the horizontal direction beyond the two boundaries;
and
one or more second contacts to the second active area.

7 more elements

A method comprising:

forming a transistor including:
forming a first source/drain region in a first active area;
forming a second source/drain region in a second active area;
forming a gate above a channel structure between the first source/drain region and the second source/drain region, including forming the gate having a horizontal length defined by and bounded by two boundaries in a horizontal direction;
direction parallel to the first source/drain region and the second source/drain region and having a width perpendicular to the horizontal length substantially bounded by the first source/drain region and the second source/drain region;
forming one or more first contacts to the first active area, with the one or more first contacts positioned above the first active area and distributed in one or more regions of the first active area along the horizontal direction beyond the two boundaries;
and
forming one or more second contacts to the second active area.

5 more elements

Dependencies are inferred from the claim text.

Contact arrangements for transistors

Life of this patent

Contact arrangements for transistors

Life of this patent

Abstract

Claims20