Integrated circuit with silicide formation blocking

Abstract

A method of forming an integrated circuit by forming a first silicon surface, forming a second silicon surface, forming a first silicide blocking layer along the first silicon surface and along the second silicon surface, and forming a second silicide blocking layer along the first silicide blocking layer. The forming of each of the first silicide blocking layer and the second silicide blocking layer includes forming a plasma enhanced chemical vapor deposition (PECVD) layer and exposing the PECVD layer to a noble gas for a time duration. Thereafter, the method removes a portion of the second silicide blocking layer and an underlying portion of the first silicide blocking layer to expose the first silicon surface while leaving at least the first silicide blocking layer over the second silicon surface and silicides the first silicon surface.

Dependencies are inferred from the claim text.