Semiconductor structure and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon Jhy Liaw
Life of this patent
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Abstract
A method includes forming a transistor comprising a channel region, a gate structure surrounding the channel region, and a plurality of source/drain regions on opposite sides of the gate structure; forming a front-side contact on a front-side of one of the source/drain regions; forming a back-side conductive via below the one of the source/drain regions, wherein the front-side contact further downwardly extends from the front-side of the one of the source/drain regions to the back-side conductive via; forming a back-side power supply voltage line connecting to the back-side conductive via.
Claims20
A method, comprising:
- forming a transistor comprising a channel region, a gate structure surrounding the channel region, and a plurality of source/drain regions on opposite sides of the gate structure;
- forming a front-side contact on a front-side of one of the source/drain regions;
- forming a back-side conductive via below the one of the source/drain regions, wherein the front-side contact further downwardly extends from the front-side of the one of the source/drain regions to the back-side conductive via, wherein the one of the source/drain regions is in contact with the back-side conductive via;
- and
- forming a back-side power supply voltage line connecting to the back-side conductive via.
A method, comprising:
- forming a plurality of first nanostructures arranged in a vertical direction;
- forming a gate strip surrounding each of the first nanostructures;
- growing a plurality of first epitaxial structures on either side of each of the first nanostructures;
- forming a dielectric layer over the first epitaxial structures;
- forming a first contact in the dielectric layer, wherein one of the first epitaxial structures is partially embedded in a back-side of the first contact;
- forming a first conductive via underlying the one of the first epitaxial structures, the first conductive via being in contact with the back-side of the first contact and having an upper surface contiguous with a bottom surface of the one of the first epitaxial structures;
- and
- forming a first power supply voltage line in contact with a back-side of the first conductive via.
A method, comprising:
- forming a plurality of nanostructures arranged in a first direction;
- forming a source/drain region adjacent the plurality of nanostructures along a second direction different than the first direction;
- forming a contact layer around the source/drain region, the contact layer extending from above the source/drain region to below the source/drain region;
- and
- forming a conductive via having an upper surface contiguous with a bottom surface of the contact layer;
- prior to forming the conductive via, forming a back-side dielectric on the bottom surface of the contact layer and a bottom surface of the source/drain region;
- and
- thinning a portion of the back-side dielectric underlying the source/drain region;
- wherein forming the conductive via comprises forming the conductive via underlying the source/drain region and separated from the source/drain region by the back-side dielectric.
Dependencies are inferred from the claim text.