Semiconductor structure and manufacturing method thereof

A method, comprising:

• forming a first fin structure of a first circuit and a second fin structure of a second circuit upwardly extending above a substrate, the first fin structure positioned adjacent the second fin structure along a first direction;
• forming a first gate electrode surrounding the first fin structure and a second gate electrode surrounding the second fin structure, the first gate electrode positioned adjacent the second gate electrode along the first direction;
• forming first source/drain regions adjoining the first fin structure and on opposite sides of the first gate electrode along a second direction different than the first direction and second source/drain regions adjoining the second fin structure and on opposite sides of the second gate electrode along the second direction from a cross sectional view;
• forming a first dielectric line isolating the first gate electrode from the second gate electrode along the first direction, the first dielectric line extending lengthwise along the second direction, the first dielectric line overlying a cell boundary between the first circuit and the second circuit, the first dielectric line having:
• a first portion extending between the first gate electrode and the second gate electrode along the first direction, the first portion contacting a first longitudinal end of the first gate electrode and a second longitudinal end of the second gate electrode from a top view;
• and
• a second portion extending between one of the first source/drain regions and one of the second source/drain regions along the first direction, the second portion adjacent the first portion along the second direction;
• wherein the first portion has a first upper surface at a first elevation relative to an upper surface of the first gate electrode, and a first lower surface at a second elevation relative to an upper surface of a first well region in the substrate under the first fin structure;
• wherein the second portion has a second upper surface at a third elevation different than the first elevation, and a second lower surface at a fourth elevation;
• and
• forming a second dielectric line in the first circuit and offset from the first dielectric line along the first direction, the second dielectric line extending lengthwise along the second direction, an upper surface of the second dielectric line being at the first elevation.

A method, comprising:

• forming a p-type transistor on a substrate, comprising:
• forming a first stack comprising a first channel layer and a second channel layer arranged over a first fin in a first direction substantially perpendicular to a top surface of the substrate;
• forming a first gate electrode extending along a second direction and wrapping around the first channel layer;
• and
• forming first source/drain regions above the substrate, wherein the first channel layer and the second channel layer extend in a third direction between the first source/drain regions;
• forming an n-type transistor on the substrate, comprising:
• forming a second stack comprising a third channel layer and a fourth channel layer arranged over a second fin in the first direction substantially perpendicular to the top surface of the substrate;
• forming a second gate electrode extending along the second direction and wrapping around the third channel layer;
• and
• forming second source/drain regions above the substrate, wherein the third channel layer and the fourth channel layer extend in the third direction between the second source/drain regions;
• forming an isolation region extending along the second direction between the first fin and the second fin;
• forming a dielectric strip extending between the p-type transistor and the n-type transistor from a top view, the dielectric strip extending toward the substrate to a depth at least as deep as depth of a bottommost surface of the isolation region;
• and
• forming a gate contact extending from the first gate electrode across the dielectric strip to the second gate electrode from the top view.