Semiconductor structure and method of forming the same

A method of forming a semiconductor structure comprising:

• forming a first stacked structure and a second stacked structure over two active regions, respectively, the two active regions being spaced apart from each other and surrounded by an isolation structure;
• forming a separating wall interconnecting the first stacked structure and the second stacked structure;
• forming a dummy gate structure over the isolation structure, the first stacked structure, the second stacked structure, and the separating wall, each of the first stacked structure, the second stacked structure and the separating wall having two portions exposed from the dummy gate structure;
• removing the two portions of the first stacked structure to form first recesses, and removing the two portions of the second stacked structure to form second recesses;
• forming a dielectric layer over the first recesses, the second recesses, the two portions of the separating wall, the isolation structure and the dummy gate structure;
• removing vertical portions of the dielectric layer, and leaving at least one of horizontal portions of the dielectric layer;
• forming first epitaxial structures in the first recesses, respectively;
• and
• forming second epitaxial structures in the second recesses, respectively.

A method of forming a semiconductor structure comprising:

• forming a semiconductor feature which includes
• a first active region and a second active region, each of which extends in a first direction, the first active region and the second active region being spaced apart from each other in a second direction different from the first direction,
• an isolation structure disposed around the first active region and the second active region,
• a patterned first stacked structure and a patterned second stacked structure that are disposed on the first active region and the second active region, respectively,
• a separating wall disposed on the isolation structure and interconnecting the patterned first stacked structure and the patterned second stacked structure, and
• a dummy gate structure extending lengthwise in the second direction, and disposed over the first active region, the second active region, the isolation structure, the patterned first stacked structure, the patterned second stacked structure and the separating wall, the first active region having two portions located on opposite sides of the dummy gate structure and exposed to first recesses, respectively, the second active region having two portions located on opposite sides of the dummy gate structure and exposed to second recesses, respectively, the separating wall having a first wall portion covered by the dummy gate structure, and two second wall portions exposed from the dummy gate structure;
• depositing a dielectric layer over the semiconductor feature;
• performing a directional treatment to treat horizontal portions of the dielectric layer;
• removing vertical portions of the dielectric layer;
• forming first epitaxial structures in the first recesses, respectively;
• and
• forming second epitaxial structures in the second recesses, respectively.