Co-integration of gate-all-around nanosheet logic device and precision mol resistor

A semiconductor structure comprising:

• a logic device region located in a first portion of a semiconductor substrate, the logic device region comprising a first gate structure wrapped around a first vertical nanosheet stack of semiconductor channel material nanosheets that is present in the logic device region, a source/drain region extending from sidewalls of each of the semiconductor channel material nanosheets of the first vertical nanosheet stack, and a bottom dielectric isolation layer separating the first gate structure and the source/drain region from the first portion of the semiconductor substrate;
• a first resistor device region located in a second portion of the semiconductor substrate, the first resistor device region comprising a second gate structure wrapped around a second vertical nanosheet stack of semiconductor channel material nanosheets that is present in the first resistor device region, a bottom dielectric isolation layer separating the second gate structure from the second portion of the semiconductor substrate, and a first metal resistor located above the second gate structure, wherein the second gate structure is a component of a non-functional nanosheet device;
• and
• a second resistor device region located in a third portion of the semiconductor substrate, the second resistor device region comprising a third gate structure wrapped around a third vertical nanosheet stack of semiconductor channel material nanosheets that is present in the second resistor device region, and a second metal resistor located above the third gate structure, wherein the third gate structure includes a source/drain region located beneath the second metal resistor that is present in the second resistor device region and extending outward from sidewalls of each semiconductor channel material nanosheets of the third vertical nanosheet stack, wherein the source/drain region of the third gate structure extends upward from, and is in direct physical contact with, a surface of a semiconductor sub-fin that is located beneath the third gate structure and the third vertical nanosheet stack, and wherein the semiconductor fin is in contact with the semiconductor substrate.

A semiconductor structure comprising:

• a logic device region located in a first portion of a semiconductor substrate, the logic device region comprising a first gate structure wrapped around a first vertical nanosheet stack of semiconductor channel material nanosheets that is present in the logic device region, a source/drain region extending from sidewalls of each of the semiconductor channel material nanosheets of the first vertical nanosheet stack, and a bottom dielectric isolation layer separating the first gate structure and the source/drain region from the first portion of the semiconductor substrate;
• and
• a resistor device region located in a second portion of the semiconductor substrate, the resistor device region comprising a second gate structure wrapped around a second vertical nanosheet stack of semiconductor channel material nanosheets that is present in the resistor device region, and a metal resistor located above the second gate structure, wherein the second gate structure includes a source/drain region located beneath the metal resistor that is present in the resistor device region and extending outward from sidewalls of each semiconductor channel material nanosheets of the second vertical nanosheet stack, wherein the source/drain region of the second gate structure extends upward from, and is in direct physical contact with, a surface of a semiconductor sub-fin that is located beneath the second gate structure and the second vertical nanosheet stack, and wherein the semiconductor sub-fin is in contact with the semiconductor substrate.