Semiconductor memory devices and methods of fabricating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMeng-Han Lin, Chia-En Huang, Sai-Hooi Yeong
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Abstract
A semiconductor device includes a word line (WL) structure. The semiconductor device includes a ferroelectric layer over the WL structure. The semiconductor device includes a channel layer over the ferroelectric layer. The semiconductor device includes a source line (SL) structure over the channel layer. The semiconductor device includes a bit line (BL) structure over the channel layer. The BL structure includes a portion that laterally extends toward the SL structure. The semiconductor device further includes a dielectric layer laterally interposed between the SL structure and the BL structure.
Claims20
A semiconductor device, comprising:
- a word line (WL) structure;
- a ferroelectric layer over the WL structure;
- a channel layer over the ferroelectric layer;
- a source line (SL) structure over the channel layer, wherein the SL structure has sidewalls parallel to each other and extending from a top surface of the SL structure to a bottom surface of the SL structure;
- a bit line (BL) structure over the channel layer, wherein the BL structure includes a portion laterally extending toward the SL structure;
- a first dielectric layer laterally interposed between the SL structure and the BL structure;
- and
- a second dielectric layer laterally interposed between the SL structure and the BL structure, wherein the first dielectric layer is disposed between the channel layer and the second dielectric layers,
- wherein a top surface of the portion of the BL structure is coplanar with the top surface of the SL structure and a top surface of the second dielectric layer.
A semiconductor device, comprising:
- a ferroelectric memory cell, including:
- a word line (WL) structure;
- a ferroelectric layer over the WL structure;
- a channel layer over the ferroelectric layer;
- a first dielectric layer over the channel layer;
- an etch-stop layer over a portion of the first dielectric layer;
- a second dielectric layer over the etch-stop layer, wherein the second dielectric layer has a composition different from the etch-stop layer;
- a source line (SL) structure over the channel layer;
- and
- a bit line (BL) structure over the channel layer and partially extending over the first dielectric layer toward the SL structure, wherein the second dielectric layer extends to contact a sidewall of each of the SL structure and the BL structure, and
- wherein a top surface of the second dielectric layer, a top surface of the SL structure, and a top surface of the BL structure are coplanar with each other.
The semiconductor device, comprising:
- a word line (WL) structure on a semiconductor substrate;
- a ferroelectric layer over the WL structure;
- a channel layer over the ferroelectric layer;
- a source line (SL) structure over the channel layer;
- a bit line (BL) structure over the channel layer;
- a first dielectric layer laterally interposed between the SL structure and the BL structure and disposed over the channel layer;
- a second dielectric layer laterally interposed between the SL structure and the BL structure, wherein the second dielectric layer extends over a portion of the first dielectric layer;
- a third dielectric layer disposed adjacent to the BL structure and over the ferroelectric layer;
- and
- a fourth dielectric layer disposed adjacent to the WL structure and between the ferroelectric layer and the semiconductor substrate,
- wherein a top surface of the third dielectric layer, a top surface of the SL structure and a top surface of the BL structure are coplanar with a top surface of the second dielectric layer.
Dependencies are inferred from the claim text.