Three-dimensional integration structure and method of forming the same

A semiconductor device, comprising:

• a first substrate layer having a first side over which devices are formed;
• a first dielectric structure formed over the first side of the first substrate layer in which the devices are positioned, the first dielectric structure including a bottom surface in direct contact with the first side of the first substrate layer, a portion of the bottom surface of the first dielectric structure not being covered by the first substrate layer;
• and
• a first electronic structure positioned over the uncovered portion of the bottom surface of the first dielectric structure such that the first electronic structure and the first substrate layer are positioned at a same side of the bottom surface of the first dielectric structure, the first electronic structure further being bonded to the first dielectric structure,
• wherein
• the devices include memory cells that further comprise:
• a stack of alternating insulating layers and word lines that is positioned over the first side of the first substrate layer in a staircase configuration and arranged in the first dielectric structure;
• a channel structure that extends through the insulating layers and the word lines;
• and
• a word line contact that is positioned over the first side of the first substrate layer and extends from one of the word lines,
• the semiconductor device further comprises:
• a first contact structure extending from the first side of the first substrate layer and extending through the first dielectric structure;
• a through silicon via (TSV) formed in the first substrate layer, the TSV extending through the first substrate layer and being in contact with the first contact structure;
• a first metal line formed over the first side of the first substrate layer and arranged on a top surface the first dielectric structure that is opposite to the bottom surface, the first metal line being coupled to one of the channel structure, the first contact structure, and the word line contact;
• and
• a pad structure positioned over and coupled to the TSV,
• the semiconductor device further comprises:
• a second dielectric structure formed over a first side of a second substrate layer, the first side of the first substrate layer and the first side of the second substrate layer being aligned;
• a transistor formed in the first side of a second substrate layer and positioned in the second dielectric structure;
• and
• a second metal line formed over the second dielectric structure and coupled to the first metal line such that the memory cells are coupled to the transistor,
• the semiconductor device further comprises:
• a source/drain (S/D) contact extending from a S/D region of the transistor;
• a gate contact extending from a gate structure of the transistor;
• and
• a second contact structure extending from the first side of the second substrate layer and extending through the second dielectric structure, wherein:
• the second metal line is coupled to one of the S/D contact, the gate contact, and the second contact structure, and
• the first metal line is coupled to the second metal line through a bonding via that is positioned between the first metal line and the second metal line, and
• the semiconductor device further comprises:
• a second electronic structure positioned over the uncovered portion of the bottom surface of the first dielectric structure and coupled to the first electronic structure, and
• a third electronic structure coupled to the transistor through the first contact structure and the second contact structure.