US 12,707,628 B2 · Memory device having 2-transistor vertical memory cell and a common plate

Abstract

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a substrate, a conductive plate located over the substrate to couple a ground connection, a data line located between the substrate and the conductive plate, a memory cell, and a conductive line. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled between the data line and the conductive plate, and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The conductive line is electrically separated from the first and second regions and spans across part of the first region of the first transistor and part of the second region of the second transistor and forming a gate of the first and second transistors.

Claims20

Dependent claims

A method comprising:

forming data lines;
forming memory cells after the data lines are formed, such that each of the memory cells includes a first transistor and a second transistor, the first transistor includes a charge storage structure located over a data line of the data lines, and a first channel region contacting the data line, the second transistor includes a second channel region between the charge storage structure and the data line;
and
forming a ground plate over the memory cells after the data lines are formed, the ground plate contacting the first channel region of the first transistor of each of the memory cells.

1 more element

A method comprising:

forming data lines over a substrate;
forming memory cells over the substrate, such that each of the memory cells includes a first transistor and a second transistor, the first transistor includes a charge storage structure located over a data line of the data lines, and a first channel region contacting the data line, the second transistor includes a second channel region between the charge storage structure and the data line;
forming conductive lines such that each of the conductive lines is electrically separated from the first and second channel region of a respective memory cell of the memory cells, and such that part of each of the conductive lines spans across part of each of the first and second channel regions of a respective memory cell of the memory cells;
and
forming a ground plate over the conductive lines and contacting the first channel region of the first transistor of each of the memory cells.

2 more elements

A method comprising:

forming levels of materials over a substrate;
forming first trenches in the levels of materials by removing part of the levels of materials, such that each of the first trenches includes a length in a first direction, a first side wall formed by a first portion of a remaining part of each of the levels of materials, and a second side wall formed by a second portion of the remaining part of each of the levels of materials;
forming a first dielectric on a first portion of the first side wall of each of the first trenches;
forming a first additional dielectric on a first portion of the second side wall of each of the first trenches;
forming a first semiconductor material adjacent the first dielectric and contacting a second portion of the first side wall of each of the first trenches;
forming a first additional semiconductor material adjacent the first additional dielectric and contacting a second portion of the second side wall of each of the first trenches;
forming a second dielectric between the first semiconductor material and the first additional semiconductor material in each of the first trenches;
and
forming second trenches in a second direction by removing a portion of the remaining part of each of the levels of materials, a portion of each of the first dielectric, a portion of the first additional dielectric, a portion of the second dielectric, a portion of the semiconductor material, and a portion of the additional material to form memory cells, such that a first memory cell of the memory cells includes at least part of a remaining portion of the semiconductor material, and a second memory cell of the memory cells includes at least part of a remaining portion of the additional semiconductor material.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/141,046Filed 28 Apr 2023 · division

Priority

28 Aug 2019

Published

US 2023/0269922 A124 Aug 2023

Granted

11 Aug 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G11C 11/403
Forming cells needing refreshing or charge regeneration, i.e. dynamic cells: with charge regeneration common to a multiplicity of memory cells,…
H10B 12/20
Dynamic random access memory [DRAM] devices: dRAM devices comprising floating-body transistors, e.g. floating-body cells
G11C 11/401
Using transistors: forming cells needing refreshing or charge regeneration, i.e. dynamic cells
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels

Family

Application62/892,988Us provisional application · filed 28 Aug 2019

Application17/003,037Parent of this division · filed 26 Aug 2020

US 2023/0269922 A1Pre-grant publication · published 24 Aug 2023

US 11,665,880 B2Parent of this division

US 2021/0066301 A1Published application

US 12,707,628 B2This patent

From the US filing history. Foreign family members aren’t listed.

Memory device having 2-transistor vertical memory cell and a common plate

Life of this patent

Memory device having 2-transistor vertical memory cell and a common plate

Life of this patent

Abstract

Claims20