Semiconductor device structure

A semiconductor device structure, comprising:

• a first device formed over a substrate, wherein the first device comprises a first channel structure;
• a first gate stack wrapped around the first channel structure, wherein the first gate stack comprises a first gate dielectric layer formed on a sidewall surface of the first channel structure,
• and the first gate dielectric layer has a first height along a vertical direction;
• a first S/D structure formed adjacent to the first gate stack;
• a first S/D contact structure formed on the first S/D structure;
• a second device formed over the first device, wherein the second device comprises a plurality of second nanostructures stacked in a vertical direction;
• a second gate stack wrapped around the second nanostructures, wherein the second gate stack comprises a second gate dielectric layer formed on a sidewall surface of one of the second nanostructures, wherein the second gate dielectric layer has a second height along the vertical direction, and the first height is different from the second height;
• a second S/D structure formed adjacent to the first gate stack;
• and
• a second S/D contact structure formed on the second S/D structure, wherein a portion of the first S/D contact structure is higher than a bottom surface of the second S/D contact structure.

A semiconductor device structure, comprising:

• a plurality of first nanostructures formed over a substrate, wherein the first nanostructures are stacked in a vertical direction;
• a first gate stack wrapped around the first nanostructures;
• a first inner gate spacer formed over the first nanostructures;
• a second channel structure formed over the first inner gate spacer;
• and
• a second gate stack wrapped around the second channel structure, wherein the second channel structure is separated from the first inner gate spacer by the second gate stack, and a height of one of the first nanostructures is smaller than a height of the second channel structure.