Equalization training method and apparatus, and system

An equalization training apparatus, comprising:

• a transceiver, configured to obtain a training rate of each of a downstream port and an upstream port in a target phase of equalization training, wherein the target phase is a third phase or a fourth phase of phases of the equalization training;
• and
• at least one processor, coupled with the transceiver, configured to:
• determine a target rate threshold interval within which the training rate in the target phase falls, determine, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configure the target equalization timeout period as an equalization timeout period in the target phase, wherein N rate thresholds are predetermined, N is an integer greater than or equal to 0, and a longer rate threshold interval corresponds to a longer equalization timeout period, wherein equalization training in the target phase is performed on the downstream port and the upstream port within the equalization timeout period in the target phase.

A chip, comprising:

• a register, configured to store a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods;
• a transceiver, configured to obtain a training rate of each of a downstream port and an upstream port in a target phase of equalization training, wherein the target phase is a third phase or a fourth phase of phases of the equalization training;
• and
• at least one processor, coupled with the transceiver, configured to:
• determine a target rate threshold interval within which the training rate in the target phase falls, determine, based on the correspondence between the N+1 rate threshold intervals and the N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configure the target equalization timeout period as an equalization timeout period in the target phase, wherein N rate thresholds are predetermined, N is an integer greater than or equal to 0, and a longer rate threshold interval corresponds to a longer equalization timeout period, wherein
• equalization training in the target phase is performed on the downstream port and the upstream port within the equalization timeout period in the target phase.

A communications system, comprising:

• a processing system configured to execute a system software stored in a memory of the communications system;
• a downstream port;
• an upstream port;
• wherein the downstream port and the upstream port are connected to each other through a peripheral component interconnect express (PCIe) bus or a cache coherent interconnect for accelerators (CCIX) bus;
• and
• wherein the processing system accesses the system software in the memory and executes the system software to configure the communications system to:
• obtain a training rate of each of the downstream port and the upstream port in a target phase of equalization training, wherein the target phase is a third phase or a fourth phase;
• and
• determine a target rate threshold interval within which the training rate in the target phase falls, determine, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configure the target equalization timeout period as an equalization timeout period in the target phase, wherein N rate thresholds are predetermined, N is an integer greater than or equal to 0, and a longer rate threshold interval corresponds to a longer equalization timeout period, wherein
• equalization training in the target phase is performed on the downstream port and the upstream port within the equalization timeout period in the target phase.