Error sampler circuit
AssigneeTexas Instruments Incorporated
InventorsAbishek Manian, Nithin Sathisan Poduval, Roland Nii Ofei Ribeiro
Life of this patent
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Abstract
An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.
Claims20
An equalizer circuit, comprising:
- a decision feedback equalizer (DFE) circuit having a first output and a second output;
- a sign-sign least mean squares (SS-LMS) adaptation circuit having a weight value output coupled to a plurality of buffer circuits;
- an error sampler circuit coupled to the DFE circuit and the SS-LMS adaptation circuit, the error sampler circuit comprising a common-mode feedback loop, and a master latch circuit, the master latch circuit including a slicer circuit;
- and
- a slave latch circuit coupled to the master latch circuit and the SS-LMS adaptation circuit.
An equalizer circuit, comprising:
- a decision feedback equalizer (DFE) circuit having a first output and a second output;
- a sign-sign least mean squares (SS-LMS) adaptation circuit having a weight value output coupled to the DFE circuit;
- an error sampler circuit coupled to the DFE circuit and the SS-LMS adaptation circuit, the error sampler circuit comprising a master latch circuit, and the master latch circuit including a slicer circuit;
- and
- a reference voltage source, wherein the reference voltage source comprises:
- a digital-to-analog converter (DAC) coupled to the SS-LMS adaptation circuit;
- and
- a common-mode feedback loop coupled to the DAC, the DFE circuit, and the error sampler circuit.
An equalizer circuit, comprising:
- a decision feedback equalizer (DFE) circuit having a first output and a second output;
- a sign-sign least mean squares (SS-LMS) adaptation circuit having a weight value output coupled to a plurality of buffer circuits;
- an error sampler circuit coupled to the DFE circuit and the SS-LMS adaptation circuit, the error sampler circuit comprising a master latch circuit, and the master latch circuit including a slicer circuit;
- and
- a slave latch circuit coupled to the master latch circuit and the SS-LMS adaptation circuit, wherein the slicer circuit is further configured to compare an input voltage to a reference voltage in a first phase of a clock signal.
Dependencies are inferred from the claim text.