Communication circuits including a differential to quadrature phase generator

A device, comprising:

• a transmission clock circuit that generates transmission clock signals to transmit data, the transmission clock circuit includes:
• a phase interpolator circuit that receives a first clock signal and a second clock signal and that interpolates phases for each of the first clock signal and the second clock signal to provide phase interpolated first clock signals and phase interpolated second clock signals;
• and
• a transmission differential to quadrature phase generator configured to:
• duty cycle correct each of the phase interpolated first clock signals and the phase interpolated second clock signals to provide duty cycle corrected phase interpolated first clock signals and duty cycle corrected phase interpolated second clock signals;
• and
• quadrature error correct each of the duty cycle corrected phase interpolated first clock signals and the duty cycle corrected phase interpolated second clock signals to generate the transmission clock signals, multiple clock phases, and a track signal;
• and
• a receiver clock circuit that generates receiver clock signals based on the multiple clock phases and the track signal to receive the data transmitted and to generate output data, the receiver clock circuit includes:
• a receiver differential to quadrature phase generator configured to:
• receive track signals based on the track signal;
• duty cycle correct clock phase signals based on the multiple clock phases to provide duty cycle corrected clock phase signals;
• quadrature error correct the duty cycle corrected clock phase signals to provide quadrature error corrected duty cycle corrected clock phase signals;
• and
• provide the receiver clock signals based on the quadrature error corrected duty cycle corrected clock phase signals.

A method of operating a communications circuit that includes at least one differential to quadrature phase generator, the method includes:

• generating, by a transmission clock circuit, a first clock signal and a second clock signal based on at least one clock signal;
• phase interpolating, by a phase interpolator circuit, each of the first clock signal and the second clock signal to provide phase interpolated first clock signals and phase interpolated second clock signals;
• duty cycle correcting, by a transmission differential to quadrature phase generator, each of the phase interpolated first clock signals and the phase interpolated second clock signals to provide duty cycle corrected phase interpolated first clock signals and duty cycle corrected phase interpolated second clock signals;
• quadrature error correcting, by the transmission differential to quadrature phase generator, each of the duty cycle corrected phase interpolated first clock signals and the duty cycle corrected phase interpolated second clock signals to generate transmission clock signals, multiple clock phases, and a track signal;
• transmitting data from a data transmission circuit based on the transmission clock signals;
• receiving by a receiver clock circuit, the multiple clock phases and the track signal;
• providing clock phase signals based on the multiple clock phases;
• generating, by a track circuit, track signals based on the track signal;
• duty cycle correcting, by a receiver differential to quadrature phase generator, the clock phase signals to provide duty cycle corrected clock phase signals;
• quadrature error correcting by the receiver differential to quadrature phase generator, the duty cycle corrected clock phase signals to generate receiver clock signals;
• and
• receiving the data transmitted from the data transmission circuit and outputting the data based on the receiver clock signals.