Semiconductor integrated circuit and receiver device
AssigneeKioxia Corporation
InventorHuy Cu Ngo
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a semiconductor integrated circuit includes: a first buffer including an input end to which a first signal is configured to be supplied; a first switching element including a first end coupled to an output end of the first buffer and a second end coupled to a first node; a first capacitor including a first end coupled to the first node and a grounded second end; a second switching element including a first end coupled to the first node and a second end coupled to a second node; a second buffer including an input end coupled to the second node; and a first converter configured to determine a first bit string from a first output from the second buffer. The first and second switching elements being configured to switch between states based on a first clock signal.
Claims18
A semiconductor integrated circuit comprising:
- a first buffer including an input end to which a first signal is configured to be supplied;
- a first switching element including a first end coupled to an output end of the first buffer and a second end coupled to a first node, the first switching element being configured to switch between states based on a first clock signal;
- a first capacitor including a first end coupled to the first node and a grounded second end;
- a second switching element including a first end coupled to the first node and a second end coupled to a second node, the second switching element being configured to switch between states based on the first clock signal;
- a second buffer including an input end coupled to the second node;
- a third buffer including an input end to which a second signal is configured to be supplied, the first signal and the second signal constituting differential signals;
- a third switching element including a first end coupled to an output end of the third buffer and a second end coupled to a third node, the third switching element being configured to switch between states based on the first clock signal;
- a second capacitor including a first end coupled to the third node and a grounded second end;
- a fourth switching element including a first end coupled to the third node and a second end coupled to a fourth node, the fourth switching element being configured to switch between states based on the first clock signal;
- a fourth buffer including an input end coupled to the fourth node;
- and
- a first converter configured to determine a first bit string from a first output from the second buffer and a second output from the fourth buffer.
A receiver device comprising:
- a semiconductor integrated circuit;
- and
- a processing circuit configured to process a signal output from the semiconductor integrated circuit,
- wherein the semiconductor integrated circuit includes:
- a first buffer including an input end to which a first signal is configured to be supplied;
- a first switching element including a first end coupled to an output end of the first buffer and a second end coupled to a first node, the first switching element being configured to switch between states based on a first clock signal;
- a first capacitor including a first end coupled to the first node and a grounded second end;
- a second switching element including a first end coupled to the first node and a second end coupled to a second node, the second switching element being configured to switch between states based on the first clock signal;
- a second buffer including an input end coupled to the second node;
- a third buffer including an input end to which a second signal is configured to be supplied, the first signal and the second signal constituting differential signals;
- a third switching element including a first end coupled to an output end of the third buffer and a second end coupled to a third node, the third switching element being configured to switch between states based on the first clock signal;
- a second capacitor including a first end coupled to the third node and a grounded second end;
- a fourth switching element including a first end coupled to the third node and a second end coupled to a fourth node, the fourth switching element being configured to switch between states based on the first clock signal;
- a fourth buffer including an input end coupled to the fourth node;
- and
- a first converter configured to determine a first bit string from a first output from the second buffer and a second output from the fourth buffer.
Dependencies are inferred from the claim text.