Differential latch circuit, switch driver, and digital-to-analog conversion circuit

A differential latch circuit, comprising a first-stage differential latch circuit, a second-stage differential inverter circuit, and a low-level shift circuit connected in sequence, wherein

• a pull-up terminal of a differential positive terminal of the second-stage differential inverter circuit comprises a first P-Channel Metal-Oxide-Semiconductor (PMOS) transistor and a second PMOS transistor, and a gate electrode of the first PMOS transistor is connected to a gate electrode of the second PMOS transistor;
• a source electrode of the first PMOS transistor is connected to a power supply voltage;
• a drain electrode of the first PMOS transistor is connected to a source electrode of the second PMOS transistor;
• and the gate electrode of the first PMOS transistor and the gate electrode of the second PMOS transistor are connected to a data input terminal of the differential positive terminal of the second-stage differential inverter circuit;
• and
• a pull-down terminal of the differential positive terminal of the second-stage differential inverter circuit comprises a third PMOS transistor and a first N-Channel Metal-Oxide-Semiconductor (NMOS) transistor, and a drain electrode of the third PMOS transistor and a source electrode of the first NMOS transistor are connected to each other, and are connected both to an output terminal of a level shift circuit;
• a gate electrode of the third PMOS transistor is connected to the data input terminal of the differential positive terminal of the second-stage differential inverter circuit, and a source electrode of the third PMOS transistor is connected to an output terminal of a pull-down terminal of a differential negative terminal of the second-stage differential inverter circuit;
• a drain electrode of the first NMOS transistor is connected to a drain electrode of the second PMOS transistor, and a gate electrode of the first NMOS transistor is connected to the data input terminal of the differential positive terminal of the second-stage differential inverter circuit;
• and a circuit structure of a differential negative terminal of the first-stage differential latch circuit is symmetrical to a circuit structure of a differential positive terminal of the first-stage differential latch circuit.