Amplifier with multiple, differential input pairs

An apparatus, comprising:

• a transistor having a control input and first and second current terminals, the second current terminal being an output of the apparatus;
• an amplifier having a reference voltage input, a second input coupled to the output of the apparatus, and an amplifier output, the amplifier output capable of providing a signal to the control input, the amplifier comprising:
• a first differential input pair of transistors having a first input terminal, a second input terminal, a first output terminal, and a second output terminal;
• a second differential input pair of transistors having a third input terminal, a fourth input terminal, a third output terminal, and a fourth output terminal, the first input terminal coupled to the third input terminal and to the reference voltage input, the second input terminal coupled to the fourth input terminal and to the second current terminal;
• and
• a cross-over circuit having a control input coupled to the second and fourth input terminals, the cross-over circuit capable of varying an amount of bias current through the second differential input pair of transistors based on a magnitude of a voltage on the second and fourth input terminals.

An amplifier, comprising:

• a first differential input pair of bipolar junction transistors having a first input terminal, a second input terminal, a first output terminal, and a second output terminal;
• a second differential input pair of field effect transistors having a third input terminal, a fourth input terminal, a third output terminal, and a fourth output terminal, the first input terminal coupled to the third input terminal, the second input terminal coupled to the fourth input terminal, the first output terminal coupled to the third output terminal, and the second output terminal coupled to the fourth output terminal;
• and
• a cross-over circuit having a control input coupled to the second and fourth input terminals, the cross-over circuit capable of varying an amount of bias current through the second differential input pair of field effect transistors based on a magnitude of a voltage on the second and fourth input terminals.