Flying-capacitor multi-level bridgeless totem-pole boost PFC converters with reduced zero-crossing distortion of line current

A multi-level bridgeless boost power factor correction (PFC) device, comprising:

• an inductor configured to electrically connect to an AC source providing a line voltage;
• a first set of switches, comprising two or more switches arranged in series, configured to be electrically connected to a terminal of the inductor at one end and to a negative output terminal at an opposite end;
• a second set of switches, comprising two or more switches arranged in series, configured to be electrically connected to the terminal of the inductor at one end and to a positive output terminal at an opposite end, wherein an output voltage of the multi-level bridgeless boost PFC converter is between the positive output terminal and the negative output terminal;
• one or more flying capacitors, wherein each of the one or more flying capacitors is connected between different pairs of adjacent ones of the first set of switches and corresponding adjacent ones of the second set of switches;
• a pair of slow leg synchronous rectifier switches connected in series, where a common terminal of the slow leg synchronous rectifier switches is connected to the AC source, a top terminal of an upper slow leg synchronous rectifier switch is connected to the positive output terminal and a bottom terminal of a bottom slow leg synchronous rectifier is connected to the negative output terminal;
• and
• a control circuit configured to:
• for a positive half-line cycle, drive the first set of switches to operate as boost switches, drive the second set of switches to operate as synchronous rectifier switches, and enable the bottom slow leg synchronous rectifier switches and disable the upper slow leg synchronous rectifier switches;
• and
• for a negative half-line cycle, drive the second set of switches to operate as boost switches, drive the first set of switches to operate as synchronous rectifier switches, and enable the upper slow leg synchronous rectifier switches and disable the bottom slow leg synchronous rectifier switches;
• wherein the control circuit is further configured to:
• disable the boost switches, the synchronous rectifier switches and the slow leg synchronous rectifier switches before and after a zero-crossing of the line voltage as to reduce a line current distortion around zero-crossings of the line voltage.