Faster method to prevent hybrid single level cell defects in system

A controller in communication with a memory apparatus including memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states, the memory cells grouped into blocks and operable as one of single-level cells storing one bit of data per each of the memory cells or multi-level cells storing a plurality of bits of the data per each of the memory cells, the controller configured to:

• instruct the memory apparatus to determine whether the memory cells of one of the blocks were previously used as the multi-level cells;
• and
• in response to determining the memory cells of one of the blocks were previously used as the multi-level cells and an occurrence of at least one failure to decode the data of the memory cells of the one of the blocks, determine a next usage of the memory cells of the one of the blocks as the multi-level cells only.

A method of operating a memory apparatus including memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states, the memory cells grouped into blocks and operable as one of single-level cells storing one bit of data per each of the memory cells or multi-level cells storing a plurality of bits of the data per each of the memory cells, the method comprising the steps of:

• determining whether the memory cells of one of the blocks were previously used as the multi-level cells;
• and
• in response to determining the memory cells of one of the blocks were previously used as the multi-level cells and an occurrence of at least one failure to decode the data of the memory cells of the one of the blocks, determining a next usage of the memory cells of the one of the blocks as the multi-level cells only.