Memory device including damage detection circuit and test system including the memory device

A memory device comprising:

• a memory cell array region comprising a plurality of memory cells;
• a plurality of bonding pads partially overlapping the memory cell array region in a vertical direction, the plurality of bonding pads comprising a bonding pad configured to electrically connect the memory device to an external device and a non-bonding pad configured to be electrically connected to an internal circuit of the memory device;
• a first test pattern form below the bonding pad and configured to output a first test output signal based on a test input signal;
• a second test pattern form below the non-bonding pad and configured to output a second test output signal based on the test input signal;
• and
• a damage detection circuit configured to output a test result signal indicating whether a lower region of the bonding pad has been damaged, based on comparing a first delay time of the first test output signal with a second delay time of the second test output signal.

A test system comprising:

• a memory device;
• and
• a test device configured to provide a test input signal to the memory device,
• wherein the memory device is configured to provide, to the test device, a test result signal generated based on the test input signal, and
• wherein the memory device comprises:
• a memory cell array region comprising a plurality of memory cells;
• a plurality of bonding pads partially overlapping the memory cell array region in a vertical direction, the plurality of bonding pads comprising a bonding pad configured to electrically connect the memory device to an external device and a non-bonding pad configured to be electrically connected to an internal circuit of the memory device;
• a first test pattern form below the bonding pad and configured to output a first test output signal based on the test input signal;
• a second test pattern form below the non-bonding pad and configured to output a second test output signal based on the test input signal;
• and
• a damage detection circuit configured to output the test result signal indicating whether a lower region of the bonding pad has been damaged, based on a first number of logic level transitions of the first test output signal and a second number of logic level transitions of the second test output signal.