US 12,706,169 B2Granted

Data storage device having a memory block failure anticipation system

AssigneeSanDisk Technologies LLC

InventorsYuvaraj Krishnamoorthy, Jayavel Pachamuthu

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Abstract

A data storage device includes a memory block failure anticipation system. The memory block failure anticipation system proactively detects defects in wordlines and/or memory blocks of the data storage device. To determine the presence of defects, the memory block failure anticipation system determines a failed bit count associated with one or more wordlines of a selected memory block and/or a failed bit count associated with the memory block. The failed bit count is compared against two thresholds—a block level data loss threshold and a wordline level data loss threshold. If the failed bit count exceeds the block level data loss threshold, the memory block is retired. If the failed bit count exceeds the wordline level data loss threshold but not the block level data loss threshold, a particular wordline of the memory block is retired and/or the memory block is retired.

Claims20

Dependent claims

A method, comprising:

selecting a memory block from a pool of free memory blocks;
initiating an erase operation on the memory block;
determining whether a program/erase (P/E) cycle count for the memory block exceeds a P/E cycle threshold;
in response to determining the P/E cycle count for the memory block exceeds the P/E cycle threshold:
performing a read operation on a first wordline of a plurality of wordlines of the memory block;
determining whether each memory cell associated with the first wordline is in a first state or a second state;
determining whether a number of memory cells in the first state exceeds a first state threshold;
in response to determining the number of memory cells in the first state exceeds the first state threshold, marking the memory block as a failed memory block;
in response to determining the number of memory cells in the first state is less than the first state threshold, determining whether the number of memory cells in the first state exceeds a second state threshold;
and
in response to determining the number of memory cells in the first state exceeds the second state threshold, marking the first wordline as a failed wordline.

8 more elements

A data storage device, comprising:

a controller;
and
a memory block failure anticipation system associated with the controller and operable to:
initiate an erase operation on a selected memory block;
determine whether a program/erase (P/E) cycle count for the selected memory block exceeds a P/E cycle threshold;
in response to a determination that the P/E cycle count for the selected memory block exceeds the P/E cycle threshold:
determine whether each memory cell associated with a first wordline of the selected memory block is in a first state;
determine whether a number of memory cells associated with the first wordline of the selected memory block in the first state exceeds a first state threshold;
in response to a determination that the number of memory cells associated with the first wordline of the selected memory block in the first state exceeds the first state threshold, mark the selected memory block as a failed memory block;
in response to a determination that the number of memory cells associated with the first wordline of the selected memory block in the first state is less than the first state threshold, determine whether the number of memory cells associated with the first wordline of the selected memory block in the first state exceeds a second state threshold;
and
in response to a determination that the number of memory cells associated with the first wordline of the selected memory block in the first state exceeds the second state threshold, mark the first wordline as a failed wordline.

9 more elements

A data storage device, comprising:

means for determining whether a program/erase (P/E) cycle count for a memory block selected for an erase operation exceeds a P/E cycle threshold;
means for determining whether each memory cell associated with a first wordline of the selected memory block is in a first state;
means for determining whether a number of memory cells associated with the first wordline of the selected memory block in the first state exceeds a first state threshold;
means for marking the selected memory block as a failed memory block in response to a determination that the P/E cycle count for the selected memory block exceeds the P/E cycle threshold;
means for determining whether the number of memory cells associated with the first wordline of the selected memory block in the first state exceeds a second state threshold;
and
means for marking the first wordline as a failed wordline in response to a determination that the number of memory cells associated with the first wordline of the selected memory block in the first state exceeds the second state threshold.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/954,273Filed 20 Nov 2024
Published: US 2026/0141966 A121 May 2026
Granted: 11 Aug 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/3495
Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles: circuits or methods to detect or delay wearout of…
G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits
G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits