Program verify pairing in a multi-level cell memory device

A method comprising:

• initiating a current loop of a program operation, the current loop comprising (a) a program phase where a plurality of memory cells associated with a selected wordline in a block of a memory array of a memory device are programmed to respective ones of a plurality of programming levels and (b) a corresponding program verify phase;
• identifying a first sub-set of the plurality of programming levels to be verified during the program verify phase of the current loop, the first sub-set comprising two or more dynamically selected programming levels comprising at least a lowest programming level for which at least one memory cell failed to pass the program verify phase of a previous loop and a second lowest programing level for which at least one memory cell failed to pass the program verify phase of the previous loop;
• identifying memory cells of the plurality of memory cells associated with the first sub-set of the plurality of programming levels to be verified during the program verify phase;
• causing a first program verify voltage to be applied to the selected wordline during the program verify phase;
• and
• performing concurrent sensing operations on the identified memory cells of the plurality of memory cells associated with the first sub-set of the plurality programming levels to determine whether the identified memory cells were programmed to respective program verify threshold voltages corresponding to the first sub-set of the plurality of programming levels during the program phase of the current loop of the program operation.

A memory device comprising:

• a memory array;
• and
• control logic, operatively coupled with the memory array to perform operations comprising:
• initiating a current loop of a program operation, the current loop comprising (a) a program phase where a plurality of memory cells associated with a selected wordline in a block of the memory array are programmed to respective ones of a plurality of programming levels and (b) a corresponding program verify phase;
• determining whether the plurality of memory cells comprises memory cells associated with an odd number of programming levels;
• responsive to determining that the plurality of memory cells comprises memory cells associated with an odd number of programming levels, identifying one or more pairs of programming levels for which at least one memory cell failed to pass the program verify phase of a previous loop, each pair comprising two programming levels, and the one or more pairs together representing all but a remaining one of the odd number of programing levels;
• associating the remaining one of the odd number of programming levels with an additional programming level;
• and
• performing a plurality of paired verify operations during the program verify phase on memory cells associated with the one or more pairs of programming levels and on memory cells associated with the remaining one of the odd number of programming levels and the additional programming level.