Staggered triggering controller
AssigneeAnaflash Inc.
InventorsSihwan Kim, Seung-Hwan Song, Jongseuk Lee
Life of this patent
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Abstract
A non-volatile memory device comprises an array of non-volatile memory cells, a controller in communication with the non-volatile memory cell, a row driver including a plurality of high-voltage switches for applying high-voltages to non-volatile memory cells, a column driver including a plurality of sensing circuits for monitoring the data of the non-volatile memory cells; and, a plurality of time delay circuits, wherein the time delay circuit is configured to reduce peak current caused by simultaneous application of high voltages to the non-volatile memory cells or simultaneous detection of current flowing across bit lines of the non-volatile memory cells.
Claims13
A non-volatile memory device
- comprising:
- an array of non-volatile memory cells;
- a controller in communication with the non-volatile memory cell,
- a row driver including a plurality of high-voltage switches for applying high-voltages to non-volatile memory cells;
- a column driver including a plurality of sensing circuits for monitoring the data of the non-volatile memory cells;
- and,
- a plurality of time delay circuits, wherein the time delay circuit is configured to reduce peak current caused by simultaneous application of high voltages to the non-volatile memory cells or simultaneous detection of current flowing across bit lines of the non-volatile memory cells,
- wherein the sensing circuit comprises a pair of cross connected CMOS inverters in that an output node of a first CMOS inverter is coupled to an input node of a second CMOS inverter,
- wherein a PMOS circuit within the first CMOS inverter is connected to a first enable PMOS circuit in parallel and a PMOS circuit within the second CMOS inverter is connected to a second enable PMOS circuit in parallel;
- wherein (1) a NMOS circuit within the first CMOS inverter is connected to a first input NMOS circuit in series, a gate terminal of the first input NMOS circuit is connected to bit line and (2) a NMOS circuit within the second CMOS inverter is connected to a second input NMOS circuit in series, a gate terminal of the second input NMOS circuit is connected to a voltage reference line;
- and
- wherein the first and second input NMOS circuits are connected to a third NMOS circuit and a drain terminal of the third NMOS circuit is shared by the first and second input NMOS circuits.
Dependencies are inferred from the claim text.