Selective management of erase operations in memory devices that enable suspend commands

A memory device comprising:

• a memory array comprising memory cells;
• and
• control logic operatively coupled with the memory array, the control logic to perform operations comprising:
• causing, as part of a true erase sub-operation, an erase pulse to be applied to one or more sub-blocks of the memory array;
• tracking a number of suspend commands received from a processing device during time periods that a memory line of the memory array is caused to ramp towards an erase voltage of the erase pulse;
• causing, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation;
• and
• in response to the number of suspend commands satisfying a threshold criterion, sending an alert to the processing device to terminate sending suspend commands until after completion of the true erase sub-operation.

A method comprising:

• causing, by control logic of a memory device, as part of a true erase sub-operation, an erase pulse to be applied to one or more sub-blocks of a memory array;
• tracking a number of suspend commands received from a processing device, including suspend commands received while memory cells of the one or more sub-blocks are being erase;
• causing, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation;
• and
• in response to the number of suspend commands satisfying a threshold criterion, sending an alert, by the control logic, to the processing device to terminate sending suspend commands until after completion of the true erase sub-operation.