Techniques for multi-level chalcogenide memory cell programming

A memory device for operating a memory array, comprising:

• one or more processors;
• memory coupled with the one or more processors;
• and
• instructions stored in the memory and executable by the one or more processors to cause the memory device to:
• receive a first command to store a first logic state in a memory cell comprising a chalcogenide material, wherein the memory cell is for storing three or more logic states;
• apply, as part of an erase operation, an initial pulse with a first polarity to a plurality of memory cells;
• apply, as part of the erase operation and based at least in part on applying the initial pulse with the first polarity, a first pulse with a second polarity to the plurality of memory cells for a first duration to store a second logic state different from the first logic state in the plurality of memory cells, the plurality of memory cells comprising the memory cell;
• and
• apply, as part of a write operation, one or more second pulses with the first polarity to the memory cell for a second duration to store the first logic state in the memory cell, the second duration different from the first duration.

A non-transitory computer-readable medium storing code comprising instructions which, when executed by one or more processors of a device, cause the device to:

• receive a first command to store a first logic state in a memory cell comprising a chalcogenide material, wherein the memory cell is for storing three or more logic states;
• apply, as part of an erase operation, an initial pulse with a first polarity to a plurality of memory cells;
• apply, as part of the erase operation and based at least in part on applying the initial pulse with the first polarity, a first pulse with a second polarity to the plurality of memory cells for a first duration to store a second logic state different from the first logic state in the plurality of memory cells, the plurality of memory cells comprising the memory cell;
• and
• apply, as part of a write operation, one or more second pulses with the first polarity to the memory cell for a second duration to store the first logic state in the memory cell, the second duration different from the first duration.