Erase operation with electron injection for reduction of cell-to-cell interference in a memory sub-system
AssigneeMicron Technology, Inc.
InventorsHong-Yan Chen, Priya Vemparala Guruswamy, Pamela Castalino, Tomoko Ogura Iwasaki
Life of this patent
Estimating the term…
Abstract
Control logic in a memory device causes a programming pulse to be applied to a set of wordlines, where the programming pulse causes a set of electrons to be injected into a first set of gate regions and a second set of gate regions. The control logic executes a first erase sub-operation on a first subset of the set of wordlines to remove a first subset of the set of electrons from the first set of gate regions. The control logic executes a second erase sub-operation on a second subset of the set of wordlines to remove a second subset of the set of electrons from the second set of gate regions.
Claims20
A memory device comprising:
- a memory array comprising a set of memory cells;
- and
- control logic, operatively coupled with the memory array, to perform operations comprising:
- causing, during execution of an erase operation to erase a memory block associated with a set of wordlines, a programming pulse to be applied to the set of wordlines, wherein the programming pulse causes a set of electrons to be injected into a first set of gate regions and a second set of gate regions;
- executing, during the erase operation, a first erase sub-operation on a first subset of the set of wordlines to remove a first subset of the set of electrons from the first set of gate regions;
- and
- executing, during the erase operation, a second erase sub-operation on a second subset of the set of wordlines to remove a second subset of the set of electrons from the second set of gate regions.
A method comprising:
- causing, during execution of an erase operation to erase a memory block associated with a set of wordlines of a memory device, a programming pulse to be applied to the set of wordlines, wherein the programming pulse causes a set of electrons to be injected into a first set of gate regions and a second set of gate regions;
- executing, during the erase operation, a first erase sub-operation on a first subset of the set of wordlines to remove a first subset of the set of electrons from the first set of gate regions;
- and
- executing, during the erase operation, a second erase sub-operation on a second subset of the set of wordlines to remove a second subset of the set of electrons from the second set of gate regions.
A memory device comprising:
- a memory array comprising a set of memory cells;
- and
- control logic, operatively coupled with the memory array, to perform operations comprising:
- causing, during execution of an erase operation, injection of a set of electrons into a charge trap (CT) layer of the memory device;
- causing, by executing a first erase sub-operation of the erase operation, removal of a first subset of the set of electrons from the CT layer of the memory device;
- and
- causing, by executing a second erase sub-operation of the erase operation, removal of a second subset of the set of electrons from the CT layer of the memory device.
Dependencies are inferred from the claim text.