Memory and operation method thereof, and memory system

A memory system, comprising:

• one or more memories, comprising:
• a memory cell array comprising a plurality of blocks, each comprising a plurality of memory cells, wherein the plurality of blocks comprise a first block and a second block;
• bit lines coupled to the plurality of memory cells, wherein a bit line for the first block and a bit line for the second block are connected to a same sense amplifier;
• a plurality of word lines coupled to the plurality of memory cells;
• and
• a peripheral circuit coupled to the bit lines and the word lines, and configured to:
• apply, at a first time period, a first voltage to a selected word line in the plurality of word lines to turn on a cell transistor of a memory cell coupled to the selected word line;
• apply, at the first time period, a second voltage to at least one dummy word line in the plurality of word lines to turn on a cell transistor of a memory cell coupled to the at least one dummy word line;
• and
• while applying the second voltage to a first dummy word line in the first block apply the second voltage to a second dummy word line in the second block;
• and
• a memory controller coupled to the memories and configured to control the memories.

An operation method of a memory, wherein the memory comprises a memory cell array, the memory cell array comprises a plurality of memory cells, and bit lines and a plurality of word lines are coupled to the plurality of memory cells, the memory cell array comprises a plurality of blocks each comprising the plurality of memory cells, the plurality of blocks comprise a first block and a second block, and a bit line for the first block and a bit line for the second block are connected to a same sense amplifier;

• wherein the operation method comprises:
• applying, at a first time period, a first voltage to a selected word line in the plurality of word lines to turn on a cell transistor of a memory cell coupled to the selected word line;
• applying, at the first time period, a second voltage to at least one dummy word line in the plurality of word lines to turn on a cell transistor of a memory cell coupled to the at least one dummy word line;
• and
• while applying the second voltage to a first dummy word line in the first block, apply the second voltage to a second dummy word line in the second block.