Dynamic memory with long retention time
AssigneeEtron Technology, Inc.
InventorsChao-Chun Lu, Bor-Doou Rong, Chun Shiah
Life of this patent
Estimating the term…
Abstract
The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.
Claims17
A DRAM chip, comprising:
- a first sustaining voltage source outputting a first voltage level which is higher than a voltage level of a signal ONE utilized in the DRAM chip;
- and
- a DRAM cell comprising an access transistor and a storage capacitor;
- wherein the first voltage level is stored in the DRAM cell before the access transistor of the DRAM cell is turned off, and a retention time of the DRAM chip is not less than 64 ms at a reference temperature of 85° C.
A DRAM chip, comprising:
- a voltage source outputting a first voltage level which is higher than a voltage level of a signal ONE utilized in the DRAM chip;
- and
- a DRAM cell comprising an access transistor and a storage capacitor;
- wherein the voltage source is selectively coupled to the DRAM cell before the access transistor of the DRAM cell is turned off, the first voltage level is stored in the DRAM cell before the access transistor of the DRAM cell is turned off, and a retention time of the DRAM chip is not less than 64 ms at a reference temperature of 85° C.
A DRAM chip, comprising:
- a first sustaining voltage source outputting a first voltage level which is higher than a voltage level of a signal ONE utilized in the DRAM chip;
- and
- a DRAM cell comprising an access transistor and a storage capacitor;
- wherein the first voltage level is stored in the DRAM cell before the access transistor of the DRAM cell is turned off, and wherein the first voltage level is dependent on a temperature of the DRAM chip.
A DRAM chip, comprising:
- a first group of DRAM cells, each DRAM cell comprising an access transistor and a storage capacitor;
- a first group of sense amplifiers electrically coupled to the first group of DRAM cells;
- and
- a first sustaining voltage source outputting a first voltage level which is higher than a voltage level of a signal ONE utilized in the DRAM chip, wherein the first voltage level is stored in the DRAM cell before the access transistor of the DRAM cell is turned off,
- wherein a retention time of the DRAM chip is gradually changed from a first reference temperature, a second reference temperature, to a third reference temperature;
- and
- wherein the retention time of the DRAM chip at the first reference temperature, the second reference temperature and the third reference temperature is at least 1.3~2 times a JEDEC defined retention time at the first reference temperature, the second reference temperature and the third reference temperature, respectively.
Dependencies are inferred from the claim text.