Display substrate including multiple cascaded shift register units, preparation method thereof, and display device

A display substrate, comprising a display region and a peripheral region on a periphery of the display region, wherein

• a gate driving circuit is arranged in the peripheral region, and the gate driving circuit comprises multiple cascaded shift register units, at least one of the shift register units comprises at least one transistor of a first semiconductor type, at least one transistor of a second semiconductor type, and at least one capacitor, and types of the at least one transistor of the first semiconductor type and the at least one transistor of the second semiconductor type are different;
• in a direction perpendicular to the display substrate, the display substrate comprises an underlay substrate, and a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer, and a third conductive layer which are arranged on the underlay substrate;
• the first semiconductor layer at least comprises an active layer of the at least one transistor of the second semiconductor type of the at least one of the shift register units;
• the first conductive layer at least comprises a control electrode of the at least one transistor of the second semiconductor type and a first electrode of the at least one capacitor of the at least one of the shift register units;
• the second semiconductor layer at least comprises an active layer of the at least one transistor of the first semiconductor type of the at least one of the shift register units;
• the second conductive layer at least comprises a control electrode of the at least one transistor of the first semiconductor type and a second electrode of the at least one capacitor of the at least one of the shift register units;
• and
• the third conductive layer at least comprises first electrodes and second electrodes of the at least one transistor of the first semiconductor type and the at least one transistor of the second semiconductor type of the at least one of the shift register units;
• wherein the first conductive layer further comprises a first output terminal, a second output terminal and a third output terminal of the at least one of the shift register units;
• wherein the second conductive layer further comprises a control signal line;
• wherein the third conductive layer further comprises a first power line and a second power line;
• wherein the at least one of the shift register units comprises an input circuit, a first control circuit, a second control circuit, and an output circuit;
• wherein the second control circuit is connected with the first power line, the second power line, the first output terminal, and a second output terminal, and is configured to provide an effective level signal of the first power line or the second power line to the second output terminal under control of the first output terminal;
• and
• the output circuit is connected with a control signal line, the first power line, the second power line, the second output terminal, and a third output terminal, and is configured to output an effective level signal of the first power line or the second power line to the third output terminal under control of the control signal line and the second output terminal, wherein, within the time of one frame, a duration of an effective level signal provided by the third output terminal is longer than a duration of an effective level signal provided by the second output terminal.