Gate driver and display device including the same
AssigneeSamsung Display Co., Ltd.
InventorsTaegyun Kim, Jaeyong Jang, Minjae Jeong
Life of this patent
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Abstract
A gate driver includes: a first transistor configured to transmit an input signal to a control node; a third transistor including a gate connected to the control node, a first terminal configured to receive a power voltage having a level higher than a level of a second low gate voltage, and a second terminal connected to an inverting control node; a fifth transistor configured to output the second low gate voltage as a gate signal in response to a signal of the control node; and a sixth transistor configured to output a high gate voltage as the gate signal in response to a signal of the inverting control node.
Claims18
A gate driver, comprising:
- a first transistor configured to transmit an input signal to a control node;
- a third transistor including a gate connected to the control node, a first terminal configured to receive a power voltage having a level higher than a level of a second low gate voltage, and a second terminal connected to an inverting control node;
- a fifth transistor having a gate connected to the control node and configured to output the second low gate voltage as a gate signal in response to a signal of the control node;
- a sixth transistor configured to output a high gate voltage as the gate signal in response to a signal of the inverting control node;
- a seventh transistor configured to output a first low gate voltage having a level higher than the level of the second low gate voltage as a carry signal in response to the signal of the control node;
- and
- an eighth transistor configured to output the high gate voltage as the carry signal in response to the signal of the inverting control node.
A display device, comprising:
- a display panel including a plurality of pixels;
- a gate driver configured to provide a gate signal to each of the pixels;
- and
- a data driver configured to provide a data voltage to each of the pixels, wherein the gate driver includes:
- a first transistor configured to transmit an input signal to a control node;
- a third transistor including a gate connected to the control node, a first terminal configured to receive a power voltage having a level higher than a level of a second low gate voltage, and a second terminal connected to an inverting control node;
- a fifth transistor having a gate connected to the control node and configured to output the second low gate voltage as the gate signal in response to a signal of the control node;
- a sixth transistor configured to output a high gate voltage as the gate signal in response to a signal of the inverting control node;
- a seventh transistor configured to output a first low gate voltage having a level higher than the level of the second low gate voltage as a carry signal in response to the signal of the control node;
- and
- an eighth transistor configured to output the high gate voltage as the carry signal in response to the signal of the inverting control node.
Dependencies are inferred from the claim text.