Parallelized architecture for multi-dimensional data processors
AssigneeNVIDIA Corporation
InventorsYi Lu, Ching-Yu Hung, Hanjie Mei, Yen-Te Shih, Chao Lyu
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Abstract
Aspects of this technical solution can increase speed of processing in low-latency application areas, while maintaining integrity of image feature recognition at those higher speeds. For example, in image-processing environments associated with autonomous navigation (e.g., driving), a large volume of image data is to be rapidly and accurately processed to maintain reliable and up-to-date models of a physical environment. For example, embodiments in accordance with this disclosure can provide high-speed and accurate image feature recognition of input frame data beyond the capability of CPU processing or general GPU processing to achieve.
Claims20
A system, comprising:
- a plurality of processors to:
- determine that first frame data corresponds to a first time and that second frame data corresponds to a second time subsequent to the first time;
- provide the first frame data to a first processor of the plurality of processors configured to execute input arranged in two dimensions;
- provide, in parallel with the providing the first frame data to the first processor, the second frame data to a second processor of the plurality of processors configured to execute input arranged in one dimension;
- and
- execute the first processor according to the first frame data in parallel with executing the second processor according to the second frame data.
A system-on-chip (SoC), comprising:
- at least one graphics processing unit (GPU);
- and
- a plurality of processors to:
- determine that first frame data corresponds to a first time and that second frame data corresponds to a second time subsequent to the first time;
- provide the first frame data to a first processor of the plurality of processors configured to execute input arranged in two dimensions;
- provide, in parallel with the providing the first frame data to the first processor, the second frame data to a second processor of the plurality of processors configured to execute input arranged in one dimension;
- and
- execute the first processor according to the first frame data in parallel with executing the second processor according to the second frame data.
A method performed by a plurality of processors, comprising:
- determining that first frame data corresponds to a first time and that second frame data corresponds to a second time subsequent to the first time;
- providing the first frame data to a first processor of the plurality of processors configured to execute input arranged in two dimensions;
- providing, in parallel with the providing the first frame data to the first processor, the second frame data to a second processor of the plurality of processors configured to execute input arranged in one dimension;
- and
- executing the first processor according to the first frame data in parallel with executing the second processor according to the second frame data.
Dependencies are inferred from the claim text.