Hybrid machine learning architecture with neural processing unit and compute-in-memory processing elements

A neural-network-processing circuit comprising:

• a plurality of compute-in-memory (CIM) processing elements (PEs);
• a plurality of neural processing unit (NPU) PEs;
• a bus coupled to the plurality of CIM PEs and to the plurality of NPU PES;
• a global memory, wherein at least one of the plurality of CIM PEs is configured to transfer data to or receive data from at least one of the plurality of NPU PEs without the data being written to or being read from the global memory;
• bus arbitration logic coupled between the bus and the plurality of CIM PEs and between the bus and the plurality of NPU PEs;
• a digital processing circuit coupled between the bus arbitration logic and the plurality of CIM PEs and between the bus arbitration logic and the plurality of NPU PEs;
• a first first-in, first-out (FIFO) circuit coupled between the digital processing circuit and the plurality of CIM PEs;
• and
• a second FIFO circuit coupled between the digital processing circuit and the plurality of NPU PEs.