Zero padding for convolutional neural networks

An integrated circuit (IC), comprising:

• a matrix multiplication accelerator (MMA) including a first memory;
• a second memory configured to store multiple rows of an input feature map on a single line of cells of the memory, and to store a filter kernel;
• and
• a memory controller configured to:
• read multiple vectors of contiguous memory (contiguous memory vectors) of the second memory, different ones of the contiguous memory vectors corresponding to different portions of the input feature map;
• replace with null values a number N>0 of values of respective ones of the contiguous memory vectors located at either each beginning or each end of the rows of the input feature map within the respective contiguous memory vector, the number and location selected in response to a column index of an element of the filter kernel in response to which the respective contiguous memory vector is read, to generate padded contiguous memory vectors;
• and
• write the padded contiguous memory vectors to the first memory.