Mode switching circuit and method, expansion connector, and PCIe card

A mode switching method, being implemented based on a mode switching circuit,

• wherein the mode switching circuit comprises:
• a first switching circuit, a second switching circuit, a clock switching circuit, and a first bidirectional level shifter, wherein
• an input terminal of the first switching circuit is configured to be connected to a first reverse differential pin of a connector, a first output terminal of the first switching circuit is configured to be connected to a first reset in-place terminal of a peripheral component interconnect express (PCIe) device, and a second output terminal of the first switching circuit is connected to the clock switching circuit;
• the first switching circuit is configured to transmit at least one of a root complex (RC) reset signal or an RC in-place signal between the first reverse differential pin and the first reset in-place terminal, or send an endpoint (ED) differential clock signal transmitted by the first reverse differential pin to the clock switching circuit;
• a first input terminal of the second switching circuit is configured to be connected to a second reset in-place terminal of the PCIe device, a second input terminal of the second switching circuit is connected to the clock switching circuit, and an output terminal of the second switching circuit is configured to be connected to a first front differential pin of the connector;
• the second switching circuit is configured to send an RC differential clock signal to the first front differential pin, or at least one of transmit an ED reset signal or an ED in-place signal between the first front differential pin and the second reset in-place terminal;
• the clock switching circuit is configured to generate a reference clock signal sent to the PCIe device and the RC differential clock signal sent to the second switching circuit, or generate the reference clock signal sent to the PCIe device according to the ED differential clock signal;
• and
• a first set of level shifting channels of the first bidirectional level shifter is configured to transmit data between a second reverse differential pin of the connector and a first data terminal of the PCIe device, and a second set of level shifting channels of the first bidirectional level shifter is configured to transmit data between a second front differential pin of the connector and a second data terminal of the PCIe device;
• two sets of level shifting channels of the first bidirectional level shifter are capable of being configured to transmit an inter-integrated circuit (I2C) bus signal or to transmit at least one of a wake-up signal or an identification (ID) signal;
• wherein the mode switching method comprises:
• performing, in an RC interface mode, following steps:
• controlling the first switching circuit to transmit the at least one of the RC reset signal or the RC in-place signal between the first reverse differential pin of the connector and the first reset in-place terminal of the PCIe device;
• controlling the clock switching circuit to generate the reference clock signal sent to the PCIe device and the RC differential clock signal sent to the second switching circuit;
• and controlling the second switching circuit to send the RC differential clock signal to the first front differential pin of the connector;
• and
• controlling the first set of level shifting channels of the first bidirectional level shifter to transmit the I2C bus signal, and controlling the second set of level shifting channels of the first bidirectional level shifter to transmit the at least one of the wake-up signal or the ID signal;
• or
• performing, in an ED interface mode, following steps:
• controlling the first switching circuit to send the ED differential clock signal transmitted by the first reverse differential pin of the connector to the clock switching circuit;
• controlling the clock switching circuit to generate the reference clock signal sent to the PCIe device according to the ED differential clock signal;
• and controlling the second switching circuit to transmit the at least one of the ED reset signal or the ED in-place signal between the first front differential pin of the connector and the second reset in-place terminal of the PCIe device;
• and
• controlling the first set of level shifting channels of the first bidirectional level shifter to transmit the at least one of the wake-up signal or the ID signal, and controlling the second set of level shifting channels of the first bidirectional level shifter to transmit the I2C bus signal.

A peripheral component interconnect express (PCIe) card, comprising:

• a PCIe device and at least one expansion connector comprising a connector and a mode switching circuit, wherein the mode switching circuit comprises:
• a first switching circuit, a second switching circuit, a clock switching circuit, and a first bidirectional level shifter, wherein
• an input terminal of the first switching circuit is configured to be connected to a first reverse differential pin of the connector, a first output terminal of the first switching circuit is configured to be connected to a first reset in-place terminal of a peripheral component interconnect express (PCIe) device, and a second output terminal of the first switching circuit is connected to the clock switching circuit;
• the first switching circuit is configured to transmit at least one of a root complex (RC) reset signal or an RC in-place signal between the first reverse differential pin and the first reset in-place terminal, or send an endpoint (ED) differential clock signal transmitted by the first reverse differential pin to the clock switching circuit;
• a first input terminal of the second switching circuit is configured to be connected to a second reset in-place terminal of the PCIe device, a second input terminal of the second switching circuit is connected to the clock switching circuit, and an output terminal of the second switching circuit is configured to be connected to a first front differential pin of the connector;
• the second switching circuit is configured to send an RC differential clock signal to the first front differential pin, or at least one of transmit an ED reset signal or an ED in-place signal between the first front differential pin and the second reset in-place terminal;
• the clock switching circuit is configured to generate a reference clock signal sent to the PCIe device and the RC differential clock signal sent to the second switching circuit, or generate the reference clock signal sent to the PCIe device according to the ED differential clock signal;
• and
• a first set of level shifting channels of the first bidirectional level shifter is configured to transmit data between a second reverse differential pin of the connector and a first data terminal of the PCIe device, and a second set of level shifting channels of the first bidirectional level shifter is configured to transmit data between a second front differential pin of the connector and a second data terminal of the PCIe device;
• two sets of level shifting channels of the first bidirectional level shifter are capable of being configured to transmit an inter-integrated circuit (I2C) bus signal or to transmit at least one of a wake-up signal or an identification (ID) signal;
• wherein the PCIe device is provided with RC firmware and ED firmware;
• the PCIe device loads the RC firmware in an RC interface mode;
• or
• the PCIe device loads the ED firmware in an ED interface mode.