Method for extending memory isolation domain, and electronic device

An electronic device comprising:

• one or more memories configured to store one or more computer programs comprising instructions;
• and
• one or more processors coupled to the one or more memories and configured to execute the instructions to cause the electronic device to:
• allocate memories of multiple isolation domains, wherein the multiple isolation domains are in a first correspondence with N protection keys and a second correspondence with M extended page tables, wherein N and M are positive integers, and wherein at least one of N or M is greater than 1, and wherein a protection key register stores an access permission corresponding to each protection key of the N protection keys;
• determine, when a first application is allowed to access a memory of a first isolation domain, and based on the first correspondence and the second correspondence, a first protection key and a first extended page table that correspond to the first isolation domain, wherein the multiple isolation domains comprise the first isolation domain, wherein the N protection keys comprise the first protection key, and wherein the M extended page tables comprise the first extended page table;
• and
• enable, based on the first protection key and the first extended page table, access permission for the first isolation domain, for the first application to access the memory, wherein to enable the access permission, the one or more processors are configured to cause the electronic device to:
• enable, when the first extended page table is the same as a current extended page table, the access permission by setting the protection key register;
• switch, when the first extended page table is different from a current extended page table, the current extended page table to the first extended page table;
• and
• enable, when the first extended page table is different from the current extended page table, the access permission by setting the protection key register.

A chip comprising:

• one or more memories configured to store instructions;
• and
• one or more processors coupled to the one or more memories and configured to execute the instructions to cause the chip to:
• allocate memories of multiple isolation domains, wherein the multiple isolation domains are in a first correspondence with N protection keys and a second correspondence with M extended page tables, wherein N and M are positive integers, and wherein at least one of N or M is greater than 1, and wherein a protection key register stores an access permission corresponding to each protection key of the N protection keys;
• determine, when a first application is allowed to access a memory of a first isolation domain, and based on the first correspondence and the second correspondence, a first protection key and a first extended page table that correspond to the first isolation domain, wherein the multiple isolation domains comprise the first isolation domain, wherein the N protection keys comprise the first protection key, and wherein the M extended page tables comprise the first extended page table;
• and
• enable, based on the first protection key and the first extended page table, access permission for the first isolation domain, for the first application to access the memory, wherein to enable the access permission, the one or more processors are configured to cause the chip to:
• enable, when the first extended page table is the same as a current extended page table, the access permission by setting the protection key register;
• switch, when the first extended page table is different from a current extended page table, the current extended page table to the first extended page table;
• and
• enable, when the first extended page table is different from the current extended page table, the access permission by setting the protection key register.