Using retired pages history for instruction translation lookaside buffer (TLB) prefetching in processor-based devices

A processor device, comprising:

• means for determining that an instruction translation lookaside buffer (TLB) demand for a first page virtual address (VA) of a first page resulted in a miss;
• and
• means for storing a history table entry representing an association of the first page VA and a value of a last retired page VA indicator in a history table, responsive to determining that the instruction TLB demand for the first page VA resulted in a miss;
• wherein:
• the last retired page VA indicator comprises a most recent page VA of a retired instruction;
• and
• the retired instruction comprises an instruction that has been executed and committed by the processor device and is no longer speculative.

A method for using retired pages history for instruction translation lookaside buffer (TLB) prefetching, comprising:

• determining, by a history-based TLB prefetcher (HTP) circuit of a processor device, that an instruction TLB demand for a first page virtual address (VA) of a first page resulted in a miss;
• and
• responsive to determining that the instruction TLB demand for the first page VA resulted in a miss, storing, by the HTP circuit, a history table entry representing an association of the first page VA and a value of a last retired page VA indicator in a history table of the HTP circuit;
• wherein:
• the last retired page VA indicator comprises a most recent page VA of a retired instruction;
• and
• the retired instruction comprises an instruction that has been executed and committed by the processor device and is no longer speculative.