Providing location-based prefetching in processor-based devices

A method for providing location-based prefetching, comprising:

• identifying, by a location-based prefetcher circuit associated with a first cache memory device of a processor-based device, an association between a first memory address of a first memory access request and a second memory address of a subsequent second memory access request;
• determining, by the location-based prefetcher circuit, a set and a way of a second cache memory device in which data corresponding to the second memory address is stored, wherein the first cache memory device has a faster access time and a smaller capacity than the second cache memory device;
• and
• storing, by the location-based prefetcher circuit in a prefetcher array entry of a plurality of prefetcher array entries of a prefetcher array of the location-based prefetcher circuit, the first memory address as a trigger memory address of the prefetcher array entry, and a set indicator and a way indicator of the set and the way, respectively, of the second cache memory device as a target identifier of the prefetcher array entry,
• wherein the location-based prefetcher circuit is external to the second cache memory device such that storing the trigger memory address and the target identifier in the prefetcher array entry does not modify data stored in the second cache memory device.

A non-transitory computer-readable medium having stored thereon computer-executable instructions which, when executed by a processor, cause the processor to provide location-based prefetching for a first cache memory device by causing the processor to:

• identify an association between a first memory address of a first memory access request and a second memory address of a subsequent second memory access request;
• determine a set and a way of a second cache memory device in which data corresponding to the second memory address is stored, wherein the first cache memory device has a faster access time and a smaller capacity than the second cache memory device;
• and
• store, in a prefetcher array entry of a plurality of prefetcher array entries of a prefetcher array of a location-based prefetcher circuit, the first memory address as a trigger memory address of the prefetcher array entry, and a set indicator and a way indicator of the set and the way, respectively, of the second cache memory device as a target identifier of the prefetcher array entry,
• wherein the location-based prefetcher circuit is external to the second cache memory device such that storing the trigger memory address and the target identifier in the prefetcher array entry does not modify data stored in the second cache memory device.