Apparatuses, systems, and methods for error correction
OwnerYoshinori Fujiwara, Vivek Kotti +3inventors
InventorsYoshinori Fujiwara, Vivek Kotti, Christopher G. Wieduwilt, Jason M. Johnson, Kevin G. Werhane
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OwnerYoshinori Fujiwara, Vivek Kotti +3inventors
InventorsYoshinori Fujiwara, Vivek Kotti, Christopher G. Wieduwilt, Jason M. Johnson, Kevin G. Werhane
Estimating the term…
Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.
A method of operating a memory device, the method comprising:
A method of operating a memory device, the method comprising:
A memory device comprising:
Dependencies are inferred from the claim text.