Selective reliability update for error decoding

A system for decoding data stored in a memory sub-system, comprising:

• a memory device;
• and
• a processing device coupled to the memory, the processing device to perform operations comprising:
• determining that a codeword received from a memory device has errors;
• assigning, responsive to the determining, a reliability value to bits of the codeword for a low-density parity check (LDPC) code, wherein the LDPC code employs an irregular H matrix to decode data;
• iteratively executing decoding operations until a termination condition is met, the decoding operations comprising:
• selecting a bit in the codeword;
• determining whether to skip a reliability update for the selected bit in the codeword based on a collated skipping pattern, a column weight of the selected bit and an iteration count of the decoding operations, wherein the collated skipping pattern is tuned using a cost function that balances correction capability and decoder latency and the cost function is defined to consider correction capability, decoder latency and bit error rate, with adjustable scalar values to prioritize either correction capability or decoding speed;
• updating the reliability value of the selected bit based on computed check node messages responsive to the selected bit not being skipped, and omitting the updating responsive to the selected bit being skipped;
• and
• determining whether each parity check defined in the LDPC code is satisfied based on updated reliability values of the bits in the codeword;
• and
• outputting a corrected codeword based on final reliability values of the bits in the codeword.

A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

• determining by an error-handling module of a controller, that a codeword received from a memory device has errors;
• assigning, by the error-handling module responsive to the determining, a reliability value to bits of the codeword for a low-density parity check (LDPC) code, wherein the LDPC code employs an irregular H matrix to decode data;
• iteratively executing decoding operations until a termination condition is met, the decoding operations comprising:
• selecting a bit in the codeword;
• determining whether to skip a reliability update for the selected bit in the codeword based on a collated skipping pattern, a column weight of the selected bit and an iteration count of the decoding operations, wherein the collated skipping pattern is tuned using a cost function that balances correction capability and decoder latency and the cost function is defined to consider correction capability, decoder latency and bit error rate, with adjustable scalar values to prioritize either correction capability or decoding speed;
• updating the reliability value of the selected bit based on computed check node messages responsive to the selected bit not being skipped, and omitting the updating responsive to the selected bit being skipped;
• and
• determining whether each parity check defined in the LDPC code is satisfied based on an updated reliability values of the bits in the codeword;
• and
• outputting a corrected codeword based on final reliability values.