Pausing memory system based on critical event
AssigneeMicron Technology, Inc.
InventorsNoorshaheen Mavungal Noorudheen, Sudhakar Ravindra Parab, Sanjay Tanaji Shinde
Life of this patent
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Abstract
Aspects of the present disclosure configure a system component, such as memory sub-system controller, to pause memory sub-system operations in response to a critical event. The memory sub-system controller can include a front-end (FE) device that stores critical event trigger data in trigger event logic registers. Upon detecting that operations of the memory sub-system, such as command latencies, correspond to the critical event trigger data, the FE device performs pause operations, including storing a state of the memory sub-system and transmitting an interrupt signal to the memory sub-system controller, such as a CPU, to initiate debugging operations.
Claims20
A system comprising:
- a memory sub-system comprising a front-end (FE) device and a set of memory components;
- and
- a processing device, operatively coupled to the FE device and the set of memory components, the memory sub-system comprising one or more components comprising a middle management logic (MML) device and a media controller (MC), the MML device receiving commands from the FE device and transmitting requests to the MC to perform the received commands, the MML device comprising command identifier logic and the FE device comprising a command queue in which the commands are stored, the FE device programmed to perform operations comprising:
- storing trigger data in storage of the FE device;
- determining that one or more operations of the memory sub-system correspond to the trigger data;
- and
- in response to determining that the one or more operations of the memory sub-system correspond to the trigger data, transmitting a signal to the processing device comprising a state of the memory sub-system.
A method comprising:
- storing trigger data in storage of a front-end (FE) device of a memory sub-system, the memory sub-system comprising one or more components comprising a middle management logic (MML) device and a media controller (MC), the MML device configured to receive receiving commands from the FE device and transmitting requests to the MC to perform the received commands, the MML device comprising command identifier logic and the FE device comprising a command queue in which the commands are stored;
- determining that one or more operations of the memory sub-system correspond to the trigger data;
- and
- in response to determining that the one or more operations of the memory sub-system correspond to the trigger data, transmitting a signal to a processing device comprising a state of the memory sub-system.
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
- storing trigger data in storage of a front-end (FE) device of a memory sub-system, the memory sub-system comprising one or more components comprising a middle management logic (MML) device and a media controller (MC), the MML device configured to receive receiving commands from the FE device and transmitting requests to the MC to perform the received commands, the MML device comprising command identifier logic and the FE device comprising a command queue in which the commands are stored;
- determining that one or more operations of the memory sub-system correspond to the trigger data;
- and
- in response to determining that the one or more operations of the memory sub-system correspond to the trigger data, transmitting a signal to the processing device comprising a state of the memory sub-system.
Dependencies are inferred from the claim text.