Tracking buffer reduction and reuse in a processor
AssigneeArm Limited
InventorsRune Holm, Jens Olson, Jared Corey Smolens, Dominic Hugo Symes, Elliot Maurice Simon Rosemarine
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AssigneeArm Limited
InventorsRune Holm, Jens Olson, Jared Corey Smolens, Dominic Hugo Symes, Elliot Maurice Simon Rosemarine
Estimating the term…
A processor comprising: a handling unit; a plurality of components each configured to execute a function. The handling unit can receive a task comprising operations on data in a coordinate space having N dimensions, receive a data structure describing execution of the task and comprising a partially ordered set of data items each associated with instructions usable by the plurality of components when executing the task, each data item is associated with a component among the plurality of components, each data item indicates dimensions of the coordinates space for which changes of coordinate causes the function of the associated component to execute, and dimensions of the coordinate space for which changes of coordinate causes the function of the associated component to store data ready to be used by another component. The handling unit iterates over the coordinate space and executes the task using the partially ordered set of data items.
A processor comprising:
A method of generating a data structure usable for execution of a task comprising operations on data in a coordinate space having N=>1 dimensions, the task configured for execution on a processor comprising a plurality of components, each component configured to execute a function, wherein the processor further comprises a storage accessible to the plurality of components and a handling circuitry, the handling circuitry configured to iterate over the N=>1 dimensional coordinate space and executing the task using the plurality of components based on a received data structure, the method comprising:
A method performed by a processor, the processor comprising a plurality of components, each component configured to execute a function and a storage accessible to the plurality of components, the method comprising:
A non-transitory computer-readable storage medium comprising a set of computer-readable instructions stored thereon which, when executed by at least one processor comprising a plurality a plurality of components, each component configured to execute a function and a storage accessible to the plurality of components, the instructions are arranged to cause the at least one processor to:
Dependencies are inferred from the claim text.