Circuitry and methods for implementing capabilities using narrow registers

A method comprising:

• decoding, by a decoder circuit of a processor core, a single instruction into a decoded single instruction, the single instruction comprising fields to indicate a memory address that stores a capability comprising an address field, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of an address space to which the capability authorizes access, a single destination register, and an opcode to indicate that an execution circuit of the processor core is to load a first proper subset of the address field and the bounds field of the capability from the memory address into the single destination register and load a second proper subset of the address field and the bounds field of the capability from the memory address into an implicit second destination register;
• executing, by the execution circuit, the decoded single instruction according to the opcode;
• checking, by a capability management circuit of the processor core, the capability in the single destination register and the implicit second destination register for a memory access request;
• decoding, by the decoder circuit, a second single instruction into a decoded second single instruction, the second single instruction comprising fields to indicate a second memory address to store a second capability and a single source register, and an opcode to indicate that the execution circuit is to store a first proper subset of an address field and a bounds field of the second capability from the single source register to the second memory address and a second proper subset of the address field and the bounds field of the second capability from an implicit second source register to the second memory address;
• and
• executing, by the execution circuit, the decoded second single instruction according to its opcode.

A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:

• decoding, by a decoder circuit of a processor core, a single instruction into a decoded single instruction, the single instruction comprising fields to indicate a memory address that stores a capability comprising an address field, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of an address space to which the capability authorizes access, a single destination register, and an opcode to indicate that an execution circuit of the processor core is to load a first proper subset of the address field and the bounds field of the capability from the memory address into the single destination register, load a second proper subset of the address field and the bounds field of the capability from the memory address into an implicit second destination register, and load a value of the validity field from the memory address into an implicit third destination register;
• executing, by the execution circuit, the decoded single instruction according to the opcode;
• and
• checking, by a capability management circuit of the processor core, the capability in the single destination register and the implicit second destination register for a memory access request.