Predication techniques
AssigneeArm Limited
InventorsAlejandro Martinez Vicente, Nigel John Stephens, Jelena Milanovic
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Abstract
Apparatuses, methods and programs are disclosed relating to the predication of multiple vectors in vector processing. An encoding of predicate information is disclosed which comprises an element size and an element count, wherein the predicate information comprises a multiplicity of consecutive identical predication indicators given by the element count, each predication indicator corresponding to the element size.
Claims20
Apparatus comprising:
- decode circuitry configured to decode instructions;
- and
- processing circuitry configured to apply vector processing operations specified by the instructions to input data vectors,
- wherein the decode circuitry is responsive to a vector processing instruction specifying:
- a vector processing operation;
- one or more source operands;
- and
- a source predicate register,
- to generate control signals which cause the processing circuitry to perform the vector processing operation with respect to the source operand, wherein the control signals further cause the processing circuitry selectively to apply the vector processing operation to elements of the one or more source operands predicated by predication indicators decoded from a predicate data value retrieved from the source predicate register,
- wherein the predicate data value has an encoding comprising:
- an element size;
- and
- an element count indicating a multiplicity of consecutive identical predication indicators, each predication indicator corresponding to the element size.
A method of data processing comprising:
- decoding instructions;
- and
- controlling processing circuitry to apply vector processing operations specified by the instructions to input data vectors,
- wherein the decoding comprises, in response to a vector processing instruction specifying:
- a vector processing operation;
- one or more source operands;
- and
- a source predicate register,
- generating control signals which cause the processing circuitry to perform the vector processing operation with respect to the source operand, wherein the control signals further cause the processing circuitry selectively to apply the vector processing operation to elements of the one or more source operands predicated by predication indicators decoded from a predicate data value retrieved from the source predicate register,
- wherein the predicate data value has an encoding comprising:
- an element size;
- and
- an element count indicating a multiplicity consecutive identical predication indicators, each predication indicator corresponding to the element size.
A non-transitory computer-readable storage medium storing a computer program for controlling a host processing apparatus to provide an instruction execution environment, the computer program comprising:
- decode logic to decode instructions;
- and
- processing logic to apply vector processing operations specified by the instructions to input data vectors,
- wherein the decode logic is responsive to a vector processing instruction specifying:
- a vector processing operation;
- one or more source operands;
- and
- a source predicate register,
- to generate control signals which cause the processing logic to perform the vector processing operation with respect to source operands, wherein the control signals further cause the processing circuitry selectively to apply the vector processing operation to elements of the one or more source operands predicated by predication indicators decoded from a predicate data value retrieved from the source predicate register,
- wherein the predicate data value has an encoding comprising:
- an element size;
- and
- an element count indicating a multiplicity of consecutive identical predication indicators, each predication indicator corresponding to the element size.
Dependencies are inferred from the claim text.