Integrated circuits with machine learning extensions

A system, comprising:

• a processor;
• and
• a programmable logic device coupled to the processor, wherein the programmable logic device comprises:
• one or more memory to store instructions to program an array of processing elements to perform computations;
• and
• the array of processing elements, wherein the array of processing elements comprises:
• a first processing element of the array of processing elements, wherein the first processing element comprises:
• a first multiplier configurable to output a first product;
• and
• a first adder configurable to combine the first product and an input to the first processing element;
• and
• a second processing element, wherein the second processing element comprises:
• a second multiplier configurable to output a second product;
• and
• a second adder configurable to combine the second product and an output from the first adder, wherein the first and second processing elements are operable to receive eight-bit inputs in an integer mode, an input in a first floating point mode, and an input in a second floating point mode, wherein the input in the first floating point mode comprises eight exponent bits, and the input in the second floating point mode comprises five exponent bits.

A system, comprising:

• a processor;
• input/output devices to input data to and output data from the processor;
• a network interface to enable the processor to interface with a network;
• memory coupled to the processor;
• a co-processor, coupled to the processor, wherein the co-processor comprises:
• an array of processing elements to perform computations, wherein the array of processing elements comprises:
• a first processing element of the array of processing elements, wherein the first processing element comprises:
• a first multiplier configurable to output a first product;
• and
• a first adder configurable to combine the first product and an input to the first processing element;
• and
• a second processing element, wherein the second processing element comprises:
• a second multiplier configurable to output a second product;
• and
• a second adder configurable to combine the second product and an output from the first adder, wherein the first and second processing elements are operable to receive eight-bit inputs in an integer mode, an input in a first floating point mode, and an input in a second floating point mode, wherein the input in the first floating point mode comprises eight exponent bits, and the input in the second floating point mode comprises five exponent bits.