Sensing within an embedded dynamic random access memories (DRAMs) having reference cells

A memory system, comprising:

• a dynamic random access memory (DRAM) array having a plurality of DRAM bit cells, each with a capacitive storage element, wherein a first portion of the DRAM array is configured as a data array and a second portion of the DRAM array is configured as a reference array, the DRAM array comprising:
• read bit lines including a first plurality of read bit lines in the data array and a second plurality of read bit lines in the reference array;
• and
• read circuitry having a plurality of sensing circuits, each sensing circuit of the plurality of sensing circuits coupled to a corresponding read bit line of the first plurality of read bit lines and configured to receive a first reference voltage generated by a first read bit line of the second plurality of read bit lines and a second reference voltage generated by a second read bit line of the second plurality of bit lines, wherein the plurality of sensing circuits is configured to provide a corresponding bit of an output read value,
• wherein each sensing circuit comprises a first stage configured to sense a first difference between a voltage on the corresponding read bit line and the first reference voltage and a second difference between the voltage on the corresponding read bit line and the second reference voltage, and a second stage configured to provide the corresponding bit of the output read value from a selected bit cell of the data array coupled to the corresponding read bit line based on the first and second differences,
• wherein the reference array is configured such that each reference bit cell of the reference array coupled to the first read bit line has a storage node that is continuously driven to a first logic state and each reference bit cell of the reference array coupled to the second read bit line has a storage node that is continuously written to a second logic state, different from the first logic state.

A memory system, comprising:

• a dynamic random access memory (DRAM) array having a plurality of DRAM cells, each with a capacitive storage element, wherein a first portion of the DRAM array is configured as a data array and a second portion of the DRAM array is configured as a reference array, the DRAM comprising:
• read bit lines including a first plurality of read bit lines in the data array and a second plurality of read bit lines in the reference array, wherein each bit cell in the reference array coupled to a first read bit line of the second plurality of bit lines has a corresponding storage node driven to a first logic state and each bit cell in the reference array coupled to a second read bit line of the second plurality of bit lines has a corresponding storage node driven to a second logic state, opposite the first logic state;
• a plurality of read word lines coupled to bit cells of the data array and reference bit cells of the reference array;
• a first plurality of write word lines coupled to the bit cells of the data array;
• and
• a second plurality of write word lines coupled to the reference bit cells of the reference array and segmented from the first plurality of write word lines, wherein all word lines of the second plurality of word lines are continuously activated while reads and writes are occurring in the data array;
• and
• read circuitry having a plurality of sensing circuits, each sensing circuit of the plurality of sensing circuits coupled to a corresponding read bit line of the first plurality of read bit lines, the first read bit line, and the second read bit line, wherein the plurality of sensing circuits is configured to provide a corresponding bit of an output read value.

In a dynamic random access memory (DRAM) array having a plurality of DRAM cells, each with a capacitive storage element, wherein a first portion of the DRAM array is configured as a data array and a second portion of the DRAM array is configured as a reference array, a method comprising:

• continuously writing reference bit cells in the reference array coupled to a first read bit line of the reference array to a first logic state and reference bit cells in the reference array coupled to a second read bit line of the reference array to a second logic state, different from the first logic state;
• and
• performing a read operation, wherein the read operation includes:
• sensing read bit lines corresponding to a set of addressed bit cells of the data array, and
• comparing a sensed voltage of each of the read bit lines corresponding to the addressed bit cells of the data array to a first reference voltage generated by the first read bit line and to a second reference voltage generated by the second read bit line to generate an output read value for the read operation corresponding to stored states of the set of addressed bit cells of the data array.