Back to results
US 12,704,543 B2Granted
Wafer analyzing device and wafer analyzing system
AssigneeSK hynix Inc.
InventorTae Beom Kim
Life of this patent
Estimating the term…
Abstract
A semiconductor wafer analyzing device and semiconductor wafer analyzing system are disclosed that provide estimated analysis values of unit areas that are not measured in a target wafer. The device and system calculate estimated analysis values based on measured analysis values of unit areas in a basic wafer and measured analysis values of some unit areas in the target wafer.
Claims20
A wafer analyzing device comprising:
- an analysis value acquiring module configured to obtain first measured analysis values for an integer N number of unit areas included in a first wafer, and to obtain second measured analysis values for an integer K number of reference unit areas, from among an N number of unit areas included in a second wafer, wherein N>K≥2;
- and
- an analysis value calculating module configured to classify a plurality of remaining unit areas included in the second wafer, wherein the plurality of remaining unit areas includes up to an (N−K) number and excludes the K number of reference unit areas, into a K number of groups, and configured to calculate an estimated analysis value for each of the up to (N−K) number of the plurality of remaining unit areas using the first measured analysis values for the integer N number of unit areas from the first wafer and the second measured analysis values for an integer K number of reference unit areas from the second wafer.
A wafer analyzing device comprising:
- an analysis value acquiring module configured to acquire an integer P number of first measured analysis values for a P number of unit areas from among an integer N number of unit areas included in a first wafer, and to acquire an integer K number of second measured analysis values of a K number of unit areas from among an N number of unit areas included in a second wafer, wherein N≥P≥2 and P>K;
- and
- an analysis value calculating module configured to calculate an estimated analysis value for each of an (N−K) number of unit areas in the second wafer, excluding the K number of unit areas having measured analysis values, based on the P number of first measured analysis values from the first wafer and the K number of second measured analysis values from the second wafer.
A wafer analyzing system comprising:
- an analyzing device configured to provide an analysis value for each of an N number of unit areas included in a target wafer;
- a testing device configured to perform a test on a plurality of semiconductor chips disposed respectively on the N number of unit areas included in the target wafer, and to provide a defect percentage for each of the N number of unit areas included in the target wafer according to the tests;
- and
- a verifying device configured to extract a cause of a defect associated with the tests based on a correlation between the analysis value of each of the N number of unit areas in the target wafer and the defect percentage of each of the N number of unit areas in the target wafer.
1 more element
Dependencies are inferred from the claim text.