Semiconductor package

A semiconductor package, comprising:

• a semiconductor substrate;
• substrate connection terminals on a bottom surface of the semiconductor substrate;
• lower semiconductor chips vertically stacked on the semiconductor substrate;
• non-conductive layers filling spaces between adjacent ones of the lower semiconductor chips;
• an upper semiconductor chip on the lower semiconductor chips;
• and
• a mold layer enclosing the lower semiconductor chips, the non-conductive layers, and the upper semiconductor chip, on the semiconductor substrate,
• wherein the mold layer fills a space between the upper semiconductor chip and an uppermost one of the lower semiconductor chips,
• wherein each of the non-conductive layers protrudes to a region on a side surface of an adjacent lower semiconductor chip of the lower semiconductor chips and is spaced apart from the upper semiconductor chip, and
• wherein the non-conductive layers comprise a material different from a material of the mold layer.

A semiconductor package, comprising:

• a first semiconductor chip;
• substrate connection terminals on a bottom surface of the first semiconductor chip;
• second semiconductor chips stacked on the first semiconductor chip;
• non-conductive layers between adjacent ones of the second semiconductor chips;
• a third semiconductor chip on the second semiconductor chips;
• connection terminals between adjacent ones of the first semiconductor chip, the second semiconductor chips, and the third semiconductor chip;
• penetration electrodes penetrating each of the first semiconductor chip and the second semiconductor chips and coupled to the connection terminals;
• and
• a mold layer enclosing the second semiconductor chips, the third semiconductor chip, and the non-conductive layers, on the first semiconductor chip,
• wherein the mold layer fills a space between the first semiconductor chip and a lowermost one of the second semiconductor chips and a space between the third semiconductor chip and an uppermost one of the second semiconductor chips,
• wherein each of the non-conductive layers comprises a protruding portion that is extended to a region on a side surface of an adjacent second semiconductor chip of the second semiconductor chips, and
• wherein each of the non-conductive layers is spaced apart from at least one of the first semiconductor chip and the third semiconductor chip.