Three-dimensional semiconductor package having a stacked passive device
AssigneeAdvanced Micro Devices, Inc.
InventorsRahul Agarwal, Raja Swaminathan
Life of this patent
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Abstract
A three-dimensional semiconductor package assembly includes a die. The die includes a plurality of through silicon vias (TSVs). The TSVs includes a first TSV and a second TSV. The first TSV supplies power from an active surface of the die to a back surface of the die. The assembly also includes a passive device coupled to the back surface of the die such that conductive contacts of the passive device electrically interface with the TSVs. The first passive device receives power through the first TSV and supplies power to the first die through the second TSV.
Claims20
A semiconductor package assembly comprising:
- a first die including a first TSV (Through Silicon Via) and a second TSV, wherein the first TSV supplies power received at a first surface of the first die to a second surface of the first die;
- a first passive device coupled to the second surface of the first die such that conductive contacts of the first passive device electrically interface with the first and second TSV, wherein the first passive device receives power supplied through the first TSV and supplies power to the first die through the second TSV, wherein the second TSV terminates at a power bus positioned within the first die between the first surface and the second surface;
- and
- a second die coupled to the second surface of the first die such that conductive contacts of the second die electrically interface with a third TSV and a fourth TSV included in the first die, wherein the third TSV terminates at the power bus, and wherein the second die receives power supplied from the first passive device through a pathway that sequentially includes the second TSV, the power bus, and the third TSV.
An apparatus comprising:
- a substrate;
- and
- a semiconductor package assembly mounted on the substrate, the semiconductor package assembly comprising:
- a first die including a first TSV (Through Silicon Via) and a second TSV, wherein the first TSV supplies power received from the substrate at an first surface of the first die to a second surface of the first die;
- a first passive device coupled to the second surface of the first die such that conductive contacts of the first passive device electrically interface with the first TSV and second TSV, wherein the first passive device receives power through the first TSV and supplies power to the first die through the second TSV, wherein the second TSV terminates at a power bus positioned within the first die between the first surface and the second surface;
- and
- a second die coupled to the second surface of the first die such that conductive contacts of the second die electrically interface with a third TSV and a fourth TSV included in the first die, wherein the third TSV terminates at the power bus, and wherein the second die receives power supplied from the first passive device through a pathway that sequentially includes the second TSV, the power bus, and the third TSV.
Dependencies are inferred from the claim text.