Semiconductor package and method of manufacturing the semiconductor package

A semiconductor package, comprising:

• at least one semiconductor chip;
• a frame surrounding the at least one semiconductor chip and having conductive connectors;
• a lower redistribution wiring layer arranged on a lower surface of the frame and having first redistribution wirings electrically connected to chip pads of the at least one semiconductor chip and the conductive connectors;
• and
• an upper redistribution wiring layer arranged on an upper surface of the frame, the upper redistribution wiring layer including at least one upper insulating layer on the frame having second redistribution wirings electrically connected to the conductive connectors of the frame, a protective layer provided on the at least one upper insulating layer and having an opening that exposes at least a portion of an uppermost redistribution wiring among the second redistribution wirings, and a bonding pad provided on the protective layer and electrically connected to the uppermost redistribution wiring through the opening of the protective layer,
• wherein the bonding pad includes:
• a first plating pattern having a via pattern filling the opening of the protective layer and a pad pattern exposed from the opening on the via pattern,
• a second plating pattern on the first plating pattern, and
• a third plating pattern on the second plating pattern, and
• wherein the second plating pattern covers an upper surface and a side surface of the first plating pattern exposed through the opening.

A semiconductor package, comprising:

• a lower redistribution wiring layer including first redistribution wirings;
• a semiconductor chip disposed on the lower redistribution wiring layer and electrically connected to the first redistribution wirings;
• a support member surrounding the semiconductor chip on the lower redistribution wiring layer;
• and
• an upper redistribution wiring layer disposed on the support member, the upper redistribution wiring layer including a sealing layer covering the semiconductor chip, at least one upper insulating layer on the sealing layer having second redistribution wirings electrically connected to conductive structures of the support member, a protective layer provided on the at least one upper insulating layer and having an opening that exposes at least a portion of an uppermost redistribution wiring among the second redistribution wirings, and a bonding pad provided on the protective layer and electrically connected to the uppermost redistribution wiring through the opening of the protective layer,
• wherein the bonding pad includes,
• a first plating pattern formed on the uppermost redistribution wiring, the first plating pattern including a via pattern provided in the opening and a pad pattern formed on the via pattern to be exposed from the opening;
• a second plating pattern formed on the first plating pattern;
• and
• a third plating pattern formed on the second plating pattern,
• wherein the second plating pattern covers an upper surface and a side surface of the first plating pattern exposed through the opening.