Substrate-on-die package architecture
AssigneeTexas Instruments Incorporated
InventorsRajen Murugan, Yiqi Tang, Sylvester Ankamah-Kusi
Life of this patent
Estimating the term…
Abstract
A packaged semiconductor device includes a lead frame and a semiconductor die. The semiconductor die has first and second opposing sides, and the first side of the die is mounted to the lead frame. A first set of bond wires and/or bump bonds are configured to electrically couple the die to the lead frame. A passive circuit element is on a substrate, and the substrate is mounted to the second side of the die. A second set of bond wires and/or bump bonds are configured to electrically couple the passive circuit element to the die. A molding material is configured to encapsulate the passive circuit element, the die, and at least a portion of the lead frame.
Claims21
A packaged semiconductor device comprising:
- a lead frame;
- a semiconductor die having first and second opposing sides, the first side of the die mounted to the lead frame;
- a first set of bond wires and/or bump bonds configured to electrically couple the die to the lead frame;
- a substrate-based passive circuit element mounted to the second side of the die;
- a second set of bond wires and/or bump bonds configured to electrically couple the passive circuit element to the die;
- and
- a molding material configured to encapsulate the passive circuit element, the die, and at least a portion of the lead frame.
A method of fabricating a packaged semiconductor device, the method comprising:
- mounting a substrate-based passive circuit element to a first side of a semiconductor die;
- mounting a second side of the semiconductor die to a die pad of a lead frame, the second side being opposite the first side;
- electrically coupling the substrate-based passive circuit element, the die, and the lead frame;
- and
- encapsulating the substrate-based passive circuit element, the die, and at least a portion of the lead frame in a molding material.
A packaged semiconductor device comprising:
- a quad flat no-lead (QFN) or quad flat package (QFP) lead frame having a die pad and a plurality of bond pads;
- a semiconductor die having first and second surfaces on opposite sides of the die, in which the second surface includes bond pads and the first surface is mounted to the die pad;
- bond wires or bump bonds electrically coupled between the bond pads of the die and bond pads of the lead frame;
- an interdigital capacitor having capacitor terminals on a routable lead frame substrate, in which the interdigital capacitor terminals are electrically coupled to bond pads of the die and the substrate is mounted to the second side of the die;
- and
- a molding material encapsulating the inter-digital capacitor device, the die, and at least a portion of the lead frame.
Dependencies are inferred from the claim text.